Structure of flash memory and its operation method

Abstract

A structure of flash memory, the structure of the flash memory element is composed of a P-type substrate, a deep N-type well region arranged in the P-type substrate, a P-type well region arranged in the deep N-type well region, and a P-type well region arranged on the P-type substrate A pair of gate structures, a selection gate disposed between the pair of gate structures, and an N-type source / drain region disposed in the P-type well region on both sides of the pair of gate structures. Since every two adjacent two-gate structures share one select gate, the integration of elements can be increased.

Description

technical field [0001] The present invention relates to a memory device, and in particular to a flash memory structure and its operating method. Background technique [0002] Flash memory elements have the advantages of being able to store, read, and erase data multiple times, and the stored data will not disappear after power failure, so it has become a widely used device in personal computers and electronic devices. A non-volatile memory element. [0003] A typical flash memory device uses doped polysilicon to make a floating gate (Floating Gate) and a control gate (Control Gate). Moreover, the control gate is directly arranged on the floating gate, the floating gate and the control gate are separated by a dielectric layer, and the floating gate and the substrate are separated by a tunnel oxide (Tunnel Oxide) ( Also known as stacked gate flash memory). [0004] When writing data into the flash memory, a bias voltage is applied to the control gate and the source / drain re...

AI Technical Summary

Problems solved by technology

[0008] In the programming method of the above-mentioned double flash memory cell, after the memory cell 101a is programmed, when the memory cell 101b is programmed again, because the memory cell 101b will be affected by the programmed memory cell 101a, the programming current will change. Low, so the programming speed of memory cell 101b will be slower than that of memory cell 101a

This will cause the problem of memory cell programming asymmetry, resulting in slower memory cell operation speed.

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