Microreglation of frequency range for delay line

Abstract

A delay line, in accordance with the invention, includes a plurality of delay elements connecting an input and an output, the delay elements for causing a delay to be introduced to a signal passing through the delay elements. A voltage device is included for regulating power to the plurality of delay elements, the voltage device being adjustable to provide at least one predetermined voltage to the delay elements such that the delay in the delay elements is modified according to the predetermined voltage(s). The delay line may be employed in a delay locked loop, a clock circuit or other circuits.

Description

technical field [0001] The present disclosure relates to delay lines, and more particularly to an apparatus for fine-tuning the frequency range of a data path employing a delay-locked closed-loop circuit with down sort capability. Background technique [0002] A delay-locked closed-loop circuit (DLL) is capable of comparing a periodic input signal with an output signal. In this way, the phase difference of the two signals can be close to zero. Referring to FIG. 1 is a conventional DLL 10 . The input signal CKin is input to the delay line 12 and the phase comparator 14 . The output signal CKout is compared with the input signal CKin by using a phase comparator 14 . The delay line 12 is adjusted by the phase comparator 14 so that the phase difference between the input signal and the output signal is zero. When the delay between the input signal CKin and the output signal CKout reaches a clock period T or its multiple KT, the delay line 12 is stable (KT, where K is a natura...

AI Technical Summary

Problems solved by technology

Also, more routing area is needed for the delay line on the chip

If there are components with short channel lengths (such as transistors) on the chip, then the requirements for low-frequency operation in JEDEC are very difficult to meet

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