Multiple high speed buffer storage line writing back and canceling technology

Abstract

A microprocessor apparatus is provided that enables write back and invalidation of a block of cache lines from memory. The apparatus includes translation logic and execution logic. The translation logic translates a block write back and invalidate instruction into a micro instruction sequence that directs a microprocessor to write back and invalidate a block of cache lines from cache to memory. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that writes back data corresponding to each of the cache lines within the block.

Description

technical field [0001] The present invention relates generally to the field of microelectronics, and more particularly to an apparatus and method that enables a programmer to instruct a microprocessor to perform write-back and invalidate operations to update a specified number of caches from an internal cache memory. memory line. Background technique [0002] Inside today's microprocessors, the speed at which data is moved between logical blocks is orders of magnitude faster than the speed at which data can be accessed in external memory. In the x86 desktop architecture, the bus that interfaces to system memory runs at a few hundred megahertz (MHz), while the internal microprocessor clock speed can run at tens of gigahertz (GHz). Thus, in recent years the cache memory hierarchy has evolved to allow high-performance microprocessors to operate at high speeds without having to traverse the low-speed memory bus every time data is read or written. [0003] The plug-in or embedd...

AI Technical Summary

Problems solved by technology

Running the instruction WBINVD will cause an unbearably long period of stalling for subsequent pending store operations

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