Microprocessor for supporting program code length reduction
A microprocessor, length reduction technology, applied in program control design, electrical digital data processing, digital data processing components and other directions, can solve problems such as address register occupation
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
no. 1 example
[0083] (a) structure
[0084] image 3 The block diagram of is showing the structure of a microprocessor of the first embodiment of the present invention. The microprocessor includes a 16-bit external address bus 212 and an 8-bit data bus 213, which is divided into a data path block 200 and an instruction decoding block 100. Note that an external memory storing instructions to be executed is not shown, but is connected to the processor through the above-mentioned bus.
[0085] The data path block 200 for transferring data or performing calculations includes a selector (SEL) 201, a register group 202, an internal bus A 203, an internal bus B 204, a decode counter (DECPC) 205, a prefetch counter (PFC) 206, Incrementer (INC) 207, Arithmetic Logic Unit (ALU) 208, Address Buffer (ADB) 209, Store Data Buffer (STB) 210 and Load Data Buffer (LDB) 211, characters in parentheses represent abbreviations. The above components have common functions.
[0086] The lengths of stack pointe...
example 1
[0115] In this example, a 5-nibble instruction stored in a location in external memory starting on a byte boundary is decoded and executed by the present microprocessor.
[0116] Figure 7A The format of the instruction is shown, which consists of a 3-nibble base instruction and two 1-nibble extension words. Signals A to E respectively represent 1-nibble codes constituting the instruction. Figure 7B shows that when instructions are stored in memory locations starting from one byte, Figure 7A Shows how the 1-nibble code for the instruction is located. Note that the alignment order of 1-nibble codes for the basic instruction word and those of the extension word are different from each other.
[0117] Figure 7C Shows how the 1-nibble code is stored in IFB 101 , IB 102 and IR 104 and what is the state of storage unit 110 on each clock cycle when the instruction decode block 100 reads the instruction. IFB101, IB102 and IR104 constitute an instruction pipeline.
[0118] In ...
example 2
[0127] In this example, a 5-nibble instruction stored in a location in external memory starting on a nibble boundary is decoded and executed by the present microprocessor.
[0128] The format of the instruction is the same as that of decoding example 1. Figure 8A shows that when instructions are stored in external memory locations starting with a nibble, Figure 7A Shows how the 1-nibble code for the instruction is located.
[0129] Figure 8B with the decoding example 1 Figure 7C Again, the data flow in the instruction pipeline is shown.
[0130] In clock cycle 1, 1-nibble code A is read into IFB101.
[0131] In clock cycle 2, 1-nibble codes B and C are read into IFB101, and 1-nibble code A is transferred into IB102. State S1 of memory cell 110 at clock cycle 2 because the last 1-nibble code of the previous instruction has been stored in a memory cell in external memory starting on a nibble boundary.
[0132] In clock cycle 3, the control unit 109 recognizes that the ...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More