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Local forming process of metal silicide layer

A silicided metal layer, local technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of no silicided metal selectivity, leakage current, affecting memory efficiency, etc.

Inactive Publication Date: 2003-03-19
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

This will cause leakage current, which will affect the efficiency of the memory
[0004] In addition, if there are other components on the substrate, such as load transistors or ESD protection devices, metal silicide will also be formed on the surface at the same time, which will cause problems
We can find that these undesired problems are caused by the non-selectivity of the traditional method to form metal silicide

Method used

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  • Local forming process of metal silicide layer
  • Local forming process of metal silicide layer
  • Local forming process of metal silicide layer

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Embodiment Construction

[0012] The present invention provides a method to form a metal silicide in a local area on an integrated circuit, which includes the following steps: first, as Figure 3A As shown, a substrate 100 is provided, on which there are at least two regions, one is the array region 101 and the other is the peripheral region 102 . A dielectric layer is deposited on the array region 101, such as a silicon oxide-silicon nitride-silicon oxide (ONO) layer 105, and a memory array is placed on the ONO layer 105, wherein adjacent word lines on the same word line There is a first space area 306 between the two memories 110 . And at least two types of components are included on the peripheral region 102: one type needs to reduce its surface resistance, such as a plurality of transistors 120; the other type does not need to reduce its surface resistance, such as a load transistor 302 in this embodiment and an electrostatic discharge protection (ESD) device 304 . Wherein, there is a second inte...

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Abstract

The present invention provides the method of forming metal silicide layer on IC locally. The method can avoid forming metal silicide on the surface of elements needing high resistance and thus has no effect of lowering the function of the elements. The method can also avoid forming metal silicide between memories in the same character line to produce leakage current. The method is mainly to form a mask on the surface of elements needing no formed metal silicide before depositing one metal layer and heating to form metal silicide.

Description

field of invention [0001] The present invention relates to a method for locally forming a metal silicide layer, in particular to a method for locally forming a metal silicide layer for avoiding the formation of a metal silicide layer on the surface of an element requiring high resistance and avoiding leakage current between memories. Background of the invention [0002] Generally, in order to reduce the resistance value and improve the efficiency of integrated circuits, a metal silicide layer, such as silicon titanium oxide, is often deposited on the surface of circuits and components. It is necessary to avoid the formation of metal silicide on the surface of the area that is not suitable for reducing the resistance value, such as the space between the memories on the same word line, and components that require high resistance values, such as load transistors (1oad transistor) and electrostatic discharge (electrostatic discharge) , ESD) protection device. Traditional format...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/283H01L21/3205
Inventor 赖二琨陈昕辉陈盈佐黄守伟黄宇萍
Owner MACRONIX INT CO LTD
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