Unlock instant, AI-driven research and patent intelligence for your innovation.

Nonvolatile semiconductor memory

A non-volatile storage and non-volatile technology, applied in semiconductor devices, static memory, read-only memory, etc., can solve the problem of increased read disturbance time

Inactive Publication Date: 2003-05-21
KK TOSHIBA
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] As described above, in order to achieve high data transfer speed, the conventional nonvolatile semiconductor memory equipped with a page mode read function has the problem of increasing the read disturbance time, and a countermeasure is required.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Nonvolatile semiconductor memory
  • Nonvolatile semiconductor memory
  • Nonvolatile semiconductor memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0175] FIG. 4 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory according to an embodiment of the present invention. The nonvolatile semiconductor memory is composed of: a memory cell array (Memory cell array) 11; a row decoder (Row decoder) 12; a column decoder (Columndecoder) 13; a block decoder 14 (Block decoder) ; column gate gate circuit (Columngate) 15; sense amplifier (Sense amp) 16; write circuit (Program circuit) 17; charge pump (Charge pump) 18; voltage switch (Voltage switch) 19; (I / O buffer) 20; controller (controller) 21; command register (Command register) 22 and address buffer (Address buffer) 23.

[0176] The address signal ADD input to the address buffer 23 is supplied to the row decoder 12 , the column decoder 13 , and the block decoder 14 respectively, and a part thereof is supplied to the command register 22 . Also, the write data WDA supplied to the I / O buffer 20 is supplied to the write circuit 17 , and the comman...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A first address subset is allocated as a first column address in a nonvolatile semiconductor memory. In addition, a second address subset higher in order than the first address subset is allocated as a first row address. Furthermore, a third address subset higher in order than the second address subset is allocated as a second column address.

Description

technical field [0001] The present invention relates to a nonvolatile semiconductor memory such as a flash memory, and particularly relates to an address assignment method for a nonvolatile semiconductor memory having a page read function. Background technique [0002] A flash memory is well known as one of the above-mentioned nonvolatile semiconductor memories. FIG. 1 is a cross-sectional view of a memory cell of the above-mentioned flash memory. This memory cell (memory cell transistor) is constituted by a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a so-called stacked gate structure in which a floating gate FG and a control gate CG are laminated with an insulating film interposed therebetween. That is, in this example, an n-type well region (N-well) 101 is formed on a p-type semiconductor substrate (P-substrate) 100, and a p-type well region (P-well) is formed in the n-type well region 101. )102. On the surface area of ​​the above-mentioned P-type...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/00G11C7/00G11C8/12G11C11/00G11C11/34G11C16/08G11C16/28G11C16/34G11C29/00H01L27/10H01L31/0328H10B69/00
CPCG11C16/08G11C16/3418G11C29/846G11C8/12H01L27/115G11C16/3436G11C16/28H10B69/00G11C16/00
Inventor 丹沢徹渥美滋
Owner KK TOSHIBA