Low power dissipation group associated cache memory adopting improved time sequency

A set-associative, low-power technology, applied in the field of multi-way set-associative high-speed cache memory, can solve the problems of adding look-up tables, increasing hardware circuit complexity, wasting datasram read power consumption, etc.

Inactive Publication Date: 2003-10-22
FUDAN UNIV
View PDF0 Cites 8 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But the shortcoming of this kind of Cache is also obvious: firstly, the hardware circuit complexity increases greatly, need to increase the hardware circuit of look-up table (look-up table); The key parameter of the processor's maximum operating frequency) is more than 60% higher than the traditional data parallel read cache, and even in the case of a cache miss, it will still read a data sram, wasting the read of the data sram power consumption

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Low power dissipation group associated cache memory adopting improved time sequency
  • Low power dissipation group associated cache memory adopting improved time sequency
  • Low power dissipation group associated cache memory adopting improved time sequency

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0024] The present invention will be described in further detail below in conjunction with the accompanying drawings.

[0025] Figure 4 Shown are the load operation timing diagrams of three different sets of associative caches, where, Figure 4 (a) is the load operation sequence of the traditional parallel read set associative cache, Figure 4 (b) is the load operation timing of PSACache, Figure 4 (c) is the load operation sequence of the set associative cache of the present invention.

[0026] The critical path circuit of load operation of the present invention sees Figure 6 Shown, timing control signal diagram see Figure 7 shown. In the following descriptions, it is assumed that the high level is the active level for the control signal. After a load cycle starts, the global address signal addr of the cache becomes the address to be read and written in this cycle, Figure 7 The middle load signal becomes high, indicating that the load operation of the cache is perf...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention is a kind of low-power consumption high-speed cache which is controlled by the improved sequence. The load operation sequence adopts that it reads each tag sarum but does not read the data sram, after that the result of tag comparator is reads the selected data scram (when cache is selected) or does not read any data sram (when cache is useless). The circuit of the invention is madeup of tag sram, data sram, tag comparator, data output multiplexer and drive circuit. The power consumption of the cache is low than conventional cache.

Description

technical field [0001] The invention relates to a low power consumption multi-way set associative cache memory (cache) designed with improved timing control. Background technique [0002] The design of low-power Cache is a bottleneck in the design of low-power processors. Since the power consumption of the cache usually accounts for a considerable part of the power consumption of the entire processor (accounting for about 20% to 50% depending on the processor and the size of the Cache), designing a low-power cache is helpful for improving processor performance and reducing the overall processor performance. The power consumption of the processor is extremely critical. Especially in recent years, the popularity of mobile electronic devices and personal communication devices (such as notebook computers and cellular phones) has made these circuit systems more urgent for low-power processors, so the design of low-power cache is extremely necessary. [0003] High-speed cache or...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/00
CPCY02B60/1225Y02D10/00
Inventor 孙慧王佳静李侠卜涛郭靖章倩苓周晓方闵昊
Owner FUDAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap