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Smooth clock switching method and clock system

A clock system and smooth switching technology, which is applied in transmission systems, digital transmission systems, automatic power control, etc., can solve the problems of clock phase mutation, clock edge difference, and high price

Inactive Publication Date: 2004-03-24
UTSTARCOM TELECOM CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Moreover, the business single disk uses a digital phase-locked loop, which is generally more expensive.
[0011] Based on the above, the following basic problems are prone to occur during the clock switching process of the traditional clock system: clock phase mutation; different single disks have clock edge differences; Transient Stability Issues

Method used

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  • Smooth clock switching method and clock system
  • Smooth clock switching method and clock system
  • Smooth clock switching method and clock system

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Embodiment Construction

[0023] The specific implementation of the technology adopted in the present invention will be described in detail below.

[0024] Figure 4 A schematic diagram of the composition of a dual-bus clock system with a phase-locked loop is shown according to the present invention.

[0025] Figure 4 It shows that the dual-bus clock system with phase-locked loop according to the present invention includes a main timing module 1 and a backup timing module 2, a clock / frame header bus and a single disk. A single disc can be multiple single discs (#1, . . . , #n). The following takes a single disk as an example for description.

[0026] A single disk includes: clock frame header detection / selection, analog phase-locked loop, phase-locked loop control module, clock edge difference detection module, frequency compensation circuit, and clock frame header distribution.

[0027] The single disk adopts the clock frame header dual-bus mode, and each timing module has a clock / frame header se...

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PUM

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Abstract

This invention discloses a method for smoothly switching clock including: detecting master clock / frame head, switching to a stand-by clock when detecting the master clock is lost. The method also includes: utilizing a timing module and two computers in a tray to generate two frame heads to carry out clock delay difference detection to their deviation and regulate the phase relationahip of the phase discrimination clock output by the said phase-locked loop to process in frequency compensation, solving the problem of transient lock lost and clock delay different among different single trays when an analog phase-locked loop is under clock switch.

Description

technical field [0001] The invention relates to a clock switching method and a clock system, in particular to a smooth clock switching method and a clock system. Background technique [0002] Devices with high clock requirements often need to configure two central timing modules, the main timing module and the standby timing module, by directly using the clock sent by the main timing module or using a phase-locked loop to track the clock sent by the main timing module , the clocks of other business single disks must be synchronized with the active timing module. [0003] Generally, the clock of the standby timing module tracks the clock of the active timing module, so the clock frequency is the same frequency, but the phase is different. [0004] When the service single disk in the system must be switched from the active clock to the standby clock, for example, when the active timing module is unplugged, the active clock It takes a certain clock period for the clock to fai...

Claims

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Application Information

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IPC IPC(8): H03L7/08H03L7/10H04L7/033
Inventor 陈罡
Owner UTSTARCOM TELECOM CO LTD