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Input and output driver

A technology of output driver and input buffer, applied in the direction of instruments, static memory, digital memory information, etc., can solve the problems of increased capacitance and difficulty in meeting the demand of input capacitance Cin

Inactive Publication Date: 2004-11-03
SK HYNIX INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Moreover, due to the increase in capacitance caused by the ODT switch transistor necessary for the ODT circuit, it is difficult to meet the demand for the input capacitance Cin

Method used

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Embodiment Construction

[0036] According to one aspect of the present invention, an input / output driver includes: an input buffer for supplying input data from a DQ contact area to a memory cell array in a write mode; an output buffer for a read mode for supplying output data from the memory cell array to the DQ contact area; and a DQ switch for electrically isolating the output driver from the DQ contact area in the write mode.

[0037] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. However, the present invention is not limited to the preferred embodiments disclosed in the following detailed description, but various changes and improvements can be made thereto. Therefore, these embodiments according to the present invention are intended to inform those skilled in the art of the art within the scope of the present invention.

[0038] figure 1 is a block diagram showing an input / output driver according to a preferred embodiment of th...

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Abstract

The present invention is provided to manufacture an input and output driver comprising a DQ switch capable of reducing a total input capacitance (Cin), by electrically isolating an output driver from a DQ pad using the DQ switch in a writing mode to reduce the capacitance due to the output driver. An input buffer supplies input data supplied from a DQ pad during a write mode to a memory cell array. An output driver supplies output data supplied from the memory cell array during a read mode to the DQ pad. And a DQ switch isolates the output driver electrically from the DQ pad during the write mode.

Description

technical field [0001] The invention relates to an input / output driver, in particular, the invention relates to an input / output driver capable of reducing the input capacitance Cin of DDR-III products with high efficiency. Background technique [0002] Double Data Rate (DDR)-III standard graphics DRAM products require a 40Ω channel impedance that supports at least 30Ω tuning. In addition, an on-dietermination (ODT) circuit provided in a GDRAM so as to match the impedance between a graphics processing unit (GPU) and a graphics DRAM (GDRAM) requires about 60Ω impedance. Also, in this GDRAM, the input capacitance Cin is limited to 3pF or less in order to ensure transmission of signal waveforms during high-speed operation of the 700MHz class. [0003] Generally, a DQ line for transmitting and receiving data is connected to complex circuit elements, such as an input buffer, an output driver, an electrostatic discharge protection circuit (hereinafter referred to as "ESD") ) and ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/10G11C11/4096
CPCG11C7/1066G11C7/1069G11C11/4096G11C2207/105G11C7/1096G11C7/1078G11C7/1051G11C7/10
Inventor 李昌烈孔明国
Owner SK HYNIX INC