FPGA logic program downloading device

Abstract

The invention discloses a FPGA logic program downloading device and method in the field of computers, adopting universal PROM, Flash, and others to compose a logic memory used in storing the FPGA logic program, and accessing the preset register contents by CPU to judge if it needs to download the FPGA logic program: if does, read the data out of the logic memory into FPGA, accordingly completing a design of downloading logic program to FPGA by CPU and at the same time, avoiding the occurrence of abnormal situations. It has a few occupied resources, simple and reliable, low-cost and short-period of implementation.

Description

technical field [0001] The invention relates to the field of computers, in particular to a method for using CPU to download FPGA logic in field programmable logic array circuits. Background technique [0002] With the development of science and technology, the cost performance of Field Programmable Logic Array FPGA (Field Programmable GateArray) is getting higher and higher, so that FPGA is widely used in more and more fields. In an FPGA circuit, an external storage unit is generally required to store the logic program of the FPGA, and the logic program is downloaded from the storage unit to the FPGA when the system is powered on or when there is a specific need, so that the FPGA can complete the designed function. There are many ways to download the logic program of the FPGA. The simpler method is to use the dedicated PROM or EEPROM provided by the FPGA manufacturer to download. The EEPROM downloads the logic program into the FPGA. The disadvantage of this method is that ...

AI Technical Summary

Problems solved by technology

However, if the CPU reads the logic program from the memory and downloads the logic to the FPGA, due to the frequent occurrence of abnormal interruption, program runaway, etc., the CPU will be reset and the CPU program will be re-executed, resulting in the system running without reloading. Download the FPGA again under power-on condition, which may lead to some abnormal situations, such as the internal registers of the FPGA are reset, and the pins of the FPGA are in a high-impedance uncertain state, which makes the system unable to work normally.

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