Circuit and method for evaluating and controlling a refresh rate of memory cells of a dynamic memory

Abstract

A circuit which is used for controlling the turnover rate of the storing unit of the dynamic memory comprises a control circuit (3) to control the access of the storing unit of the dynamic memory and can be operated with many operating modes. The storing circuit which is driven by the control circuit is used for storing the time information item relative to the access of the storing unit assigned to the time information item. The control circuit can be operated in the monitoring operating mode so that after the access of the storing unit the time information item is written to the storing circuit from the control circuit and the time information item is read out when the subsequent access to the assigned storing unit is executed. The readout time information item is sent to the evaluating circuit with this the evaluating time item, and with this way the evaluating information time item relative to the time period between individual access to the assigned storing unit can be outputted to the exterior of the memorizer. According to the circuit of the invention the turnover rate of the storing unit can be registered, monitored and modified according to the need in the monitoring operating mode.

Description

technical field [0001] The present invention relates to a circuit and method for evaluating and controlling the update rate of a dynamic memory storage unit. Background technique [0002] In integrated dynamic memories in the form of DRAMs, a so-called refresh operation is necessary during operation when the memory cell is not externally accessed to refresh the memory cell content, which may be caused by leakage current from the storage capacitor or select transistor And volatile, and thus permanently retain the memory cell content. During a refresh operation, the evaluated and amplified information signal from a selected memory cell is written back directly to the associated memory cell. This is typically controlled by a controller circuit which additionally defines the update frequency with which individual updates of the memory cell contents are actuated. [0003] There are several possibilities for updating the content of the memory unit. First, during normal operatio...

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Problems solved by technology

[0007] The disadvantage with this form of distributed updating is that, in particular, it is not possible to define when distributed updating is to be actuated, since at various points in time depending on access capacity utilization

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