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Semiconductor memory device having external data load signal and serial-to-parallel data prefetch method thereof

A technology of data loading and storage devices, which is applied in the direction of digital memory information, information storage, static memory, etc., can solve problems such as difficulties in circuit design by engineers, and achieve the effect of internal timing margin balance and high-frequency operation condition improvement

Inactive Publication Date: 2005-07-13
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Also, because of these fluctuations, it is more difficult for engineers to design circuits

Method used

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  • Semiconductor memory device having external data load signal and serial-to-parallel data prefetch method thereof
  • Semiconductor memory device having external data load signal and serial-to-parallel data prefetch method thereof
  • Semiconductor memory device having external data load signal and serial-to-parallel data prefetch method thereof

Examples

Experimental program
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Embodiment Construction

[0038] Figure 6 is a schematic block diagram for explaining a memory system according to an embodiment of the present invention. The system 50 includes a memory controller 52 for providing data and control signals to and from the memory circuit, which may be an SDRAM circuit. The storage controller 500 includes an SDRAM memory 560 and a control circuit 60 , the memory 560 includes an SDRAM memory unit and an SDRAM data input terminal, and the control circuit 60 controls the data writing operation of the SDRAM memory unit and other functions of the memory circuit 50 .

[0039] The interface between memory controller 52 and memory circuit 500 carries address (ADDR) and data (DIN) signals. It also has various control and timing signals, which can include a data strobe signal DQS, an external clock signal EXTCLK, and some commands (CMD), which can include chip select signals (CSB), row addresses Strobe signal (RASB), column address strobe signal (CASB) and write enable signal (...

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Abstract

A semiconductor memory system, a memory control circuit and a semiconductor memory device are disclosed. The system includes a memory control circuit for generating a data strobe signal and a data load signal synchronized with each other. The memory circuit may be an SDRAM memory circuit, which receives a data strobe signal and a data load signal, and writes data in response to these two synchronized signals. Parameters introduced by timing variations due to different signal domains are eliminated due to signal synchronization. As a result, the high-frequency operation of the system is greatly improved.

Description

[0001] related application [0002] The Korean priority application number of this application is 2002-27277, and the priority date is May 17, 2002, the content of which is hereby incorporated by reference. technical field [0003] The present invention generally relates to a semiconductor storage device, in particular to a synchronous semiconductor storage device with an external data loading signal, and a serial-parallel data prefetching method thereof. Background technique [0004] When SDRAM (Synchronous Dynamic Random Access Memory) is operated synchronously with an external system clock and there are frequent continuous data read / write operations, SDRAM is superior in operation speed and performance to DRAM (Dynamic Random Access Memory) which operates asynchronously. [0005] The operation speed and performance of the SDRAM can also be improved when both the rising and falling edges of the system clock are used in reading and writing data, that is, the clock rate is e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/00G06F13/16G11C7/10G11C11/407G11C11/409G11C11/4096
CPCG06F13/1689G11C7/1078G11C7/1087G11C2207/107G11C11/4096
Inventor 张星珍郭镇锡
Owner SAMSUNG ELECTRONICS CO LTD