Semiconductor memory device having external data load signal and serial-to-parallel data prefetch method thereof
A technology of data loading and storage devices, which is applied in the direction of digital memory information, information storage, static memory, etc., can solve problems such as difficulties in circuit design by engineers, and achieve the effect of internal timing margin balance and high-frequency operation condition improvement
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[0038] Figure 6 is a schematic block diagram for explaining a memory system according to an embodiment of the present invention. The system 50 includes a memory controller 52 for providing data and control signals to and from the memory circuit, which may be an SDRAM circuit. The storage controller 500 includes an SDRAM memory 560 and a control circuit 60 , the memory 560 includes an SDRAM memory unit and an SDRAM data input terminal, and the control circuit 60 controls the data writing operation of the SDRAM memory unit and other functions of the memory circuit 50 .
[0039] The interface between memory controller 52 and memory circuit 500 carries address (ADDR) and data (DIN) signals. It also has various control and timing signals, which can include a data strobe signal DQS, an external clock signal EXTCLK, and some commands (CMD), which can include chip select signals (CSB), row addresses Strobe signal (RASB), column address strobe signal (CASB) and write enable signal (...
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