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Shared code caching method and apparatus for program code conversion

A cache and code technology, applied in the direction of program control design, program control device, program loading/starting, etc., can solve problems such as inability to develop performance or market contact

Active Publication Date: 2006-08-23
IBM CORP
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Problems solved by technology

It was also found that mainstream CPU architectures were locked in time to their ISAs and were unable to advance in terms of performance or market exposure

Method used

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  • Shared code caching method and apparatus for program code conversion
  • Shared code caching method and apparatus for program code conversion
  • Shared code caching method and apparatus for program code conversion

Examples

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Embodiment Construction

[0026] Next, attach Figures 1 to 8 Clarify methods, devices, and program codes available in program code transformation. attached Figure 9 Clarifications can be used, for example, in applications such as Figure 1-8 Various aspects of the shared code caching technique in program transcoding systems illustrated in .

[0027] attached figure 1 A target processor 13 including target registers 15 is shown, as well as memory which stores a number of software components 19, 20, 21 and provides a working storage area including basic block cache 23, global register store 27 and source code 17 to be translated. The software components include the operating system 20 , the translator code 19 , and the translated code 21 . The translator code 19 may work eg as a simulator for translating source code of one ISA to translated code of another ISA or as an accelerator for translating source code to translated code of the same ISA.

[0028] Translator 19, i.e. the compiled version of t...

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Abstract

Subject program code is translated to target code (21) in basic block units at run-time in a process wherein translation of basic blocks is interleaved with execution of those translations. A shared code cache mechanism is added to persistently store subject code translations, such that a translator may reuse translations that were generated and / or optimized by earlier translator instances.

Description

technical field [0001] The present invention generally relates to the field of computers and computer software, and more particularly to methods and devices for program code conversion such as used in code translators, simulators and accelerators. Background technique [0002] In both embedded and non-embedded CPUs, one finds the popular instruction set architecture (ISA), for which there are a large number of capable processors that can be "accelerated" for performance or "translated" into multiple efficient processors. ), if these processors can transparently access the associated software, then they can exhibit a better cost / performance advantage. It was also found that mainstream CPU architectures were locked in time to their ISAs and were unable to advance in terms of performance or market exposure. This architecture would benefit from a "synthetic CPU" common architecture. [0003] Such acceleration, translation and co-architectural capabilities are facilitated by a ...

Claims

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Application Information

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IPC IPC(8): G06F9/44G06F9/45G06F9/38G06F9/445
CPCG06F9/3812G06F9/45516
Inventor 杰兰特·诺斯
Owner IBM CORP
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