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Confinement competition digital circuit with homophase displacement mode

A technology that restricts competition and shifting methods, applied to electrical components, code conversion, etc., can solve problems such as lack of feature sequences, inconvenience, and irregularity

Inactive Publication Date: 2007-02-28
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The Gray code in the prior art is mainly a kind of restrictive competition coding, and only one bit is allowed to change between each codeword. However, since the Gray code is not a weight code, when it is used for counting, Very inconvenient, without regularity, i.e. lack of characteristic sequences
If it is used for counting, corresponding registers must be set for the four sequences, so the realized circuit is more complicated

Method used

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  • Confinement competition digital circuit with homophase displacement mode
  • Confinement competition digital circuit with homophase displacement mode
  • Confinement competition digital circuit with homophase displacement mode

Examples

Experimental program
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Effect test

Embodiment 1

[0041] As shown in Figure 2, after reset, the serial input terminal Ax of the shift register 1 initializes one end of the preset switch 6 through the characteristic sequence, and serially inputs the reverse sequence of the characteristic sequence 0000000111111110 into the shift register 1 and the shift register 2 one by one to form The 16-bit register group A of the 16-bit register group A whose data is preset as the characteristic sequence 0111111110000000, the serial input terminal Ax of the shift register 3 initializes and presets one end of the switch 7 through the characteristic sequence and shifts the inverse sequence of the characteristic sequence 1100011100111000 serially one by one The 16-bit register group B composed of register 3 and shift register 4 presets its data as the characteristic sequence 0001110011100011, and the sequence of the characteristic sequence is arranged from low bit 0 to high bit 16. At this time, the code output of latch 5 is 0000, namely 0 for ...

Embodiment 2

[0045] As shown in Figure 3, the initialization is to turn on the preset tube of each latch unit by turning on the preset switch K, the shift register group A is pre-charged with a fixed characteristic sequence potential 0111111110000000 from LA0 to LA15, and the shift register group B is from LB0~LB15 are respectively precharged with a fixed characteristic sequence potential 0001110011100011, and the sequence of the characteristic sequence is from low bit 0 to high bit 16. At this time, the output code output d3d2d1d0 composed of latches LB12, LA12, LB0, and LA0 is 0000, which is the constraint 0 for the competition count code.

[0046]After the preset tubes of the shift register group A and B are turned off by the preset switch K, if it is necessary to count up, when the first pulse appears at the CLK terminal, the 16-bit data of the shift register group A is cyclically shifted to the left once, becoming 1111111100000000, the 16-bit data of the shift register group B is shif...

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Abstract

The invention relates to a constraint competition counting code circuit with in-phase shift method. Wherein, it comprises a 16-bit shift register (A), 16-bit shift register (B), 4-bit output register (C), initialize preset switch (D), initialize preset switch (E), while the highest and lowest bits of shift registers (A, B) are end-to-end connected, and the registers (A, B) are preset by the switches (D, E) into fixed character sequence; the counting impulse is connected to the shift control port (CLK) of 16-bit register; the 0 bits of registers (B, A) are connected to the lower two bits of 4-bit output latch; the twelve 12s of registers (B, A) are connected to the higher two bits of 4-bit output latch; after initialization preset, inputting impulse, using in-phase shift to count and output constraint competition counting code.

Description

technical field [0001] The invention relates to a restricted contention counting digital circuit of a hexadecimal coded in-phase shift mode with restricted contention. Background technique [0002] Hexadecimal number 8421 yards gray code bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 0 0000 0000 1 0001 0001 2 0010 0011 3 0011 0010 4 0100 0110 5 0101 0111 6 0110 0101 7 0111 0100 8 1000 1100 9 1001 1101 A 1010 1111 B 1011 1110 C 1100 1010 D 1101 1011 E 1110 1001 F 1111 1000 [0003] The Gray code in the prior art is mainly a kind of restrictive competition coding, and only one bit is allowed to change between e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M7/16H03M7/14
Inventor 李冰
Owner SOUTHEAST UNIV
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