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Cache memory analyzing method

一种缓冲存储器、高速缓冲的技术，应用在存储器系统、内存地址/分配/重定位、仪器等方向，能够解决高速缓冲存储器存取状态不得而知等问题

Active Publication Date: 2007-03-14
SOCIONEXT INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, since the access conflicts of the cache memory are statistically analyzed at compile time in this method, the access status of the cache memory in actual operation is unknown

Method used

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no. 1 example

[0053] FIG. 1 is a schematic diagram of a processor 10 and its system for outputting cache access information with cache miss address records according to an embodiment of the present invention.

[0054] In FIG. 1 , a processor 10 includes a CPU 11 , a cache memory 12 and a cache miss address output unit 13 . The cache memory 12 has a structure of a multi-way set associative system. When a cache miss occurs when data is requested from the cache memory 12 , the cache miss address output unit 13 outputs the address of the data where the miss occurred as a cache miss address to the outside of the processor. With the above configuration, the processor 10 can analyze the occupancy state of the cache memory using only the address at which the cache miss occurs.

[0055] FIG. 2 shows a simulated information processing device 20 simulating the structure shown in FIG. 1 . The emulation information processing device 20 includes a CPU 21 , a cache memory 22 and a cache miss address out...

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Abstract

What is done is to read from the cache the information containing the memory address that caused the cache miss. The number of cache misses occurring at each cache miss occurrence address included in the information is totaled. The cache miss generation addresses where the number of generated cache misses are totaled are segmented for each set. Further, a group of addresses whose numbers of generated cache misses are identical or close is extracted from a plurality of cache miss generated addresses classified as addresses in the same set.

Description

technical field [0001] The present invention relates to a cache memory analysis method for detecting cache memory access conflicts due to memory access conflicts in a processor carrying the cache memory or in a simulated information processing device simulating the processor and the like Missed. Background technique [0002] In systems such as processors or simulated information processing devices (emulators), latency due to cache misses when data is requested is one of the most serious bottlenecks. Therefore, how to reduce cache misses is important in order to improve execution performance in embedded systems operating on processors and information processing devices. In order to effectively reduce cache misses, it is necessary to designate memory access data that is highly effective in reducing cache misses in the above system. [0003] Conventionally, there is a known method (1) for specifying memory access data that is highly effective in reducing cache misses. It is ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08
CPCG06F12/0864
Inventor 山贺真纯宫下贵典加藤浩一
Owner SOCIONEXT INC
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