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Fast fourier transform circuit having partitioned memory for minimal latency during in-place computation

A Fourier transform, fast technology, applied in calculation, complex mathematical operations, electrical digital data processing, etc., can solve the problems of reducing the performance of fast Fourier transform circuits, inefficient use of storage, and increasing circuit costs

Inactive Publication Date: 2007-05-16
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the use of the butterfly unit requires a large number of repeated memory read and write operations to fetch input values ​​and store output values
Therefore, implementing an FFT architecture with any technology may result in an inefficient use of memory, and the requirement for massive memory controller resources increases circuit cost and / or degrades the performance of the FFT circuit

Method used

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  • Fast fourier transform circuit having partitioned memory for minimal latency during in-place computation
  • Fast fourier transform circuit having partitioned memory for minimal latency during in-place computation
  • Fast fourier transform circuit having partitioned memory for minimal latency during in-place computation

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Embodiment Construction

[0024] FIG. 1 is a schematic diagram of a FFT circuit 10 configured to perform FFT or inverse FFT on a prescribed number of data values ​​(data value) according to an embodiment of the present invention. The fast Fourier transform circuit 10 includes a base four (Radix-4) butterfly unit 12 (butterfly element), a memory controller 14 (memory controller) and several memory portions (memory portion), which can also be called a memory bank. (memorybank) 16a and 16b.

[0025] The radix-4 butterfly unit 12 is configured to simultaneously receive four inputs (A1, A2, B1, B2) and generate and simultaneously output four calculation results (A'1, A'2, B'1, B '2), which is based on the known radix-four butterfly operation to perform Fast Fourier Transform calculations.

[0026] The storage parts 16a and 16b are configured to store equal portions of a prescribed number of data values ​​for in-place computation operations. Specifically, assuming that a 64-point FFT is generated, each sto...

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Abstract

An FFT circuit (10) is implemented using a radix-4 butterfly element (12) and a partitioned memory (16a, 16b) for storage of a prescribed number of data values. The radix-4 butterfly element is configured for performing an FFT operation in a prescribed number of stages (30a, 30b, 30c), each stage including a prescribed number of in-place computation operations (32) relative to the prescribed number of data values. The partitioned memory includes a first memory portion and a second memory portion, and the data values (34, 36) for the FFT circuit are divided equally for storage in the first and second memory portions in a manner that ensures that each I-place computation operation is based on retrieval of an equal number of data values retrieved from each of the first and second memory portions.

Description

technical field [0001] The present invention relates to the implementation of a fast Fourier transform circuit in a real-time system, such as an Orthogonal Frequency Division Multiplexing receiver conforming to the IEEE802.11a standard. Background technique [0002] Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) have been frequently used in modern communication systems due to their efficiency in Orthogonal Frequency Division Multiplexing (OFDM) systems such as the Digital Subscriber Loop family ( xDSL) modem, high-definition television (HDTV) and wireless LAN applications. Examples of WLAN applications include wireless LANs (wireless infrastructure with fixed access points), mobile ad hoc networks, and the like. Specifically, the IEEE802.11a standard is called "Wireless Local Area Network Medium Access Control Layer (MAC) and Physical Layer (PHY) Specifications: High-speed Physical Layer in the 5GHz Band", which refers to an orthogonal branch of a wi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14
CPCG06F17/142G06F17/14
Inventor J-P·沈C-M·黄C·(R)·薛O·卡内隆斯
Owner ADVANCED MICRO DEVICES INC