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System and method for transmitting interrupt messages through a parallel communication bus

A communication bus, message technology, applied in instruments, electrical digital data processing, etc., can solve problems affecting the overall speed of computer systems, etc.

Inactive Publication Date: 2007-05-30
GENERAL ELECTRIC CO
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] The interrupt method provided by the PCI specification and other similar parallel computer buses such as VME has several deficiencies, all of which negatively affect the overall speed of the computer system

Method used

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  • System and method for transmitting interrupt messages through a parallel communication bus
  • System and method for transmitting interrupt messages through a parallel communication bus
  • System and method for transmitting interrupt messages through a parallel communication bus

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Embodiment Construction

[0011] Referring to FIG. 1 , a computer system 10 is provided. As shown, computer system 10 includes PCI bus master device 12 , PCI bus 14 , PCI bus master device 16 , PCI bus master device 18 , PCI target device 20 , and PCI target device 22 . An advantage of computer system 10 is that system 10 allows devices coupled to a parallel communication bus to send interrupt messages that identify the sending device. An interrupt signal or interrupt message causes the target device to temporarily suspend other tasks of the target device while the target device performs the task indicated by the interrupt message.

[0012] PCI host device 12 is provided to perform tasks related to facilitating communications over PCI communication bus 14 . PCI host device 12 assigns a unique address range to each device coupled to PCI communication bus 14 . In addition, the PCI bus arbiter in PCI host device 12 authorizes only one device coupled to bus 14 to initiate a data transfer on bus 14 at a p...

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Abstract

A computer system and a method for transmitting interrupt messages through a parallel communication bus are provided. The computer system includes a first device operably communicating with a second device via a parallel communication bus. The first device is configured to transmit a first interrupt message through the parallel communication bus to the second device, wherein the first interrupt message has a data portion with a plurality of bits having a first identifier identifying the first, device.

Description

Background technique [0001] Computer systems have been developed that utilize the Peripheral Component Interconnect (PCI) bus. The PCI bus requires only one PCI host device and one or more non-host PCI devices operatively coupled to the PCI bus. The PCI bus optionally includes a set of interrupt lines coupled between PCI host devices and non-PCI host devices. Any non-host PCI device can change the voltage on the interrupt line to interrupt the PCI host device, causing the PCI host device to hang whatever task it is performing, and execute the higher priority task associated with the interrupt. [0002] The interrupt method provided by the PCI specification and other similar parallel computer buses such as VME has several deficiencies, all of which negatively affect the overall speed of the computer system. Specifically, whenever one of the interrupt lines is asserted, the interrupted device must generate one or more bus cycles to determine which interrupting device asserted ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/24
CPCG06F13/24
Inventor N·达维斯D·哈特费尔德F·卡特温克尔O·N·威尔斯
Owner GENERAL ELECTRIC CO