Multi-level redistribution layer traces for reducing current crowding in flipchip solder bumps

Abstract

A multi-level redistribution layer trace reduces current crowding in solder bumps of an integrated circuit package. A multi-level redistribution layer trace for an integrated circuit die includes a redistribution layer trace formed on the integrated circuit die in each of a plurality of electrically conductive layers and an I / O pad formed at a termination of the redistribution layer trace so that the I / O pad extends through each of the plurality of electrically conductive layers to form an electrical junction between the termination of the redistribution layer trace and the I / O pad in each of the plurality of electrically conductive layers. The redistribution layer trace may also be slotted to divide current flow horizontally at the electrical junction between the termination of the redistribution layer trace and the I / O pad in each of the plurality of electrically conductive layers.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This is a divisional application of pending U.S. patent application Ser. No. 10 / 327,333 by Atila Mertol et al. for “MULTI-LEVEL REDISTRIBUTION LAYER TRACES FOR REDUCING CURRENT CROWDING IN FLIPCHIP SOLDER BUMPS”, filed on Dec. 20, 2002.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates generally to the design of flip-chip packages used in the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention relates to metal redistribution layer traces in an integrated circuit die. [0004] 2. Description of the Prior Art [0005] An important issue in microelectronic packaging is reliability. Technologies for microelectronic packaging are developed not only to manufacture microelectronic packages at low cost, but also to ensure that the performance of the microelectronic packages will not deteriorate over their service life. A critical factor in determ...

AI Technical Summary

Benefits of technology

This design significantly reduces current crowding in solder bumps, enhancing the reliability of both the die and package by diffusing current flow over a wider area, thereby extending the service life of integrated circuits.

Problems solved by technology

An important issue in microelectronic packaging is reliability.

In certain areas of the solder bumps near the junctions of the traces and the I / O pads, the current density reaches a maximum that may shorten the useful life of the integrated circuit.

It has been discovered that current crowding results in the deterioration of not only the trace junctions, which decreases the wafer level reliability, but also the solder bumps, which decreases the package level reliability.