Complementary metal-oxide semiconductor (CMOS) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same

Abstract

A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This application claims priority to Korean Patent Application No. 10-2004-0081111, filed on Oct. 11, 2004, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to semiconductor devices and methods of manufacturing the same, and, more particularly, to complementary metal-oxide semiconductor (CMOS) devices and methods of manufacturing the same. [0004] 2. Description of the Related Art [0005] Typically, a gate of metal-oxide semiconductor field effect transistors (MOSFETs) comprises polysilicon. However, because the design rule of complementary metal-oxide semiconductor (CMOS) devices is typically less than 100 nm, the use of a polysilicon gate may result in gate depletion and boron (Br) penetration. Recently, high-k materials have been used to form gate-insulating layer...

AI Technical Summary

Problems solved by technology

However, because the design rule of complementary metal-oxide semiconductor (CMOS) devices is typically less than 100 nm, the use of a polysilicon gate may result in gate depletion and boron (Br) penetration.

However, most high-k materials and polysilicon typically cannot be used together.

That is, ion implantation typically cannot be used for 3-dimentional transistors, such as a transistor with a thin body channel.

Therefore, changing the doping concentration of the channel region by using an ion implantation process typically cannot be used to control the threshold voltage of the NMOS transistor and the PMOS transistor.

Howeve

Images