Self-aligned contact for silicon-on-insulator devices
a silicon-on-insulator and self-aligning technology, applied in the direction of semiconductor devices, electrical equipment, transistors, etc., can solve the problems of gate substantially controlling the on and off state, gate oxide thickness, gate oxide thickness, and gate oxide thickness becoming increasingly difficult to meet in conventional device structures where bulk silicon substrates are used, and significant variations in the electrical characteristics of the devi
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[0033] The present invention concerns the provision of self-aligned contacts to the source and drain regions in advanced semiconductor device structures such as ultra-thin body transistors, double-gate transistors such as the finFET transistor, triple-gate transistors, and omega-FET. Transistors with two or more gates, including the double-gate transistor, the triple-gate transistor, and the omega-FET are termed “multiple-gate transistors”.
[0034] In FIG. 3A, the plane view of an improved contact scheme for the UTB transistor 50 is shown. An enlarged, cross-sectional view through the dash line B-B′ of FIG. 3A is shown in FIG. 3B. The contacts 24,26 overlap a contact spacer 36, so that any slight misalignment in the source and drain contacts 24,26 will not affect the distance between the source contact 24 and the channel region 28 and the distance between the drain contact 26 and the channel region 28. The distances between the source contact 24 or the drain contact 26 and the channe...
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