Control of processing elements in parallel processors

Inactive Publication Date: 2009-02-26
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This design reduces the number of shift operations required for data transfer, enhancing the efficiency and flexibility of data movement between processing elements, allowing for easier data exchange within the processor array.

Problems solved by technology

One problem with current system and methods of shifting data between processing elements in a processing element array is that every processing element has to send and receive data at the same time.

Method used

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  • Control of processing elements in parallel processors
  • Control of processing elements in parallel processors
  • Control of processing elements in parallel processors

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Embodiment Construction

[0125]Referring to FIG. 1, one embodiment of an active memory block in accordance with the invention is shown. Active memory block 100 includes a memory 106 and memory processors 110. Memory 106 is preferably random access memory (RAM), in particular dynamic RAM (DRAM). Memory processors 110, which include processing element (PE) arrays, can communicate with memory 106 via an interconnection block 108. The interconnection block 108 can be any suitable communications path, such as a bidirectional high memory bandwidth path. A central processing unit (CPU) 102 can communicate with active memory block 100 via a communications path 104. The communications path 104 may be any suitable bidirectional path capable of transmitting data.

[0126]Referring to FIG. 2, a processing element array 200 having multiple processing elements arranged in rows and columns is shown. The array 200 is shown as an array of 4 columns×4 rows. However, it will be appreciated that the array 200 could be scaled to l...

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Abstract

The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line connects to all of the processing elements in the column. For each row in the array, a row select line connecting to all of the processing elements in the row. A processing element in the array may be selected by activation of its row and column select lines.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of U.S. patent application Ser. No. 10 / 412,716, filed Apr. 11, 2003, which claims priority from UK Patent Application No. 0221563.0, filed Sep. 17, 2002.FIELD OF THE INVENTION[0002]The present invention relates to the control of processing elements in a parallel processor. Preferred embodiments of the present invention relate to the control of an array of processing elements in an active memory device.BACKGROUND TO THE INVENTION[0003]A simple computer generally includes a central processing unit (CPU) and a main memory. The CPU implements a sequence of operations encoded in a stored program. The program and the data on which the CPU acts are typically stored in the main memory. The processing of the program and the allocation of main memory and other resources are controlled by an operating system. In operating systems where multiple applications may share and partition resources, the processing performa...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G06F15/80G06F9/06G06F12/06G06F15/00G06F15/173
CPCG06F15/17337G06F15/8023G06F12/06
InventorKIRSCH, GRAHAM
OwnerMICRON TECH INC