Semiconductor structure processing using multiple laterally spaced laser beam spots delivering multiple blows

Abstract

Methods and systems process a semiconductor substrate having a plurality of structures to be selectively irradiated with multiple laser beams. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The method generates a first laser beam that propagates along a first laser beam axis that intersects a first target location on or within the semiconductor substrate. The method also generates a second laser beam that propagates along a second laser beam axis that intersects a second target location on or within the semiconductor substrate. The second target location is offset from the first target location in a direction perpendicular to the lengthwise direction of the rows by some amount such that, when the first target location is a structure on a first row of structures, the second target location is a structure or between two adjacent structures on a second row distinct from the first row. The method moves the semiconductor substrate relative to the first and second laser axes in a direction approximately parallel to the rows of structures, so as to pass the first target location along the first row to irradiate for a first time selected structures in the first row, and so as to simultaneously pass the second target location along the second row to irradiate for a second time structures previously irradiated by the first laser beam during a previous pass of the first target location along the second row.

Description

RELATED APPLICATIONS[0001]This application is a divisional of U.S. patent application Ser. No. 11 / 051,262, entitled “Semiconductor Structure Processing Using Multiple Laterally Spaced Laser Beam Spots Delivering Multiple Blows,” filed Feb. 4, 2005, which in turn claims priority under 35 U.S.C. §119 to U.S. Provisional Application No. 60 / 580,917, entitled “Multiple-Beam Semiconductor Link Processing,” filed Jun. 18, 2004. The entire disclosures of the foregoing documents are incorporated by reference herein.[0002]Also incorporated by reference herein are the entire disclosures of the following commonly owned U.S. patent applications filed Feb. 4, 2005: application Ser. No. 11 / 051,265, entitled “Semiconductor Structure Processing Using Multiple Laterally Spaced Laser Beam Spots with On-Axis Offset,” now U.S. Pat. No. 7,435,927; application Ser. No. 11 / 052,014, entitled “Semiconductor Structure Processing Using Multiple Laterally Spaced Laser Beam Spots with Joint Velocity Profiling”; ...

AI Technical Summary

Benefits of technology

[0017]As used herein: the term “on” means not just directly on but atop, above, over, or covering, in any way, partially or fully; the term “substantially” is a broadening term that means about or approximately

Problems solved by technology

During their fabrication process, ICs (integrated circuits) often incur defects for various reasons.

In addition, link banks, and link runs may not be straight rows and may not be processed with continuous motion.

Improvements in these areas will continue; however, practical limitations associated with these parameters make this a difficult way to achieve large throughput gains.

Increasing stage acceleration introduces additional vibrations and generates heat, both of which can decrease system accuracy.

Significantly increasing the stage acceleration and bandwidth, without diminishing the positional accuracy or increasing the system footprint, is a challenging and costly engineering endeavor, and the benefits of that effort would only be moderate.

Increasing the laser PRF, and hence link run velocity, is also undesirable for a number of reasons.

First, there are unfavorable changes in the laser pulses that result from increasing the PRF.

This may decrease the processing efficiency on some link structures.

Higher laser PRFs are also associated with less energy stability, which also decreases processing efficiency.

High laser PRFs are also undesirable when applied to semiconductor products that have a large link pitch.

Processing at high stage velocities may also not be possible if these velocities exceed some system specification, such as the maximum stage or position feedback sensor velocity.

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