Nonvolatile flash memory structures including fullerene molecules and methods for manufacturing the same

Abstract

Embodiments of tunneling barriers and methods for same can embed molecules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C₆₀ molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented. In one embodiment, the tunneling barrier can be between a floating gate and a channel in a semiconductor structure. In one embodiment, a tunneling film can be used in nonvolatile memory applications where C₆₀ provides accessible energy levels to prompt resonant tunneling through the dielectric layer upon voltage application. Embodiments also contemplate engineered fullerene molecules incorporated within the context of at least one of a tunneling dielectric and a floating gate within a nonvolatile flash memory structure.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation-in-part (CIP) application of application Ser. No. 12 / 748,253, filed Mar. 26, 2010 entitled “Nonvolatile Memory and Methods for Manufacturing the Same With Molecule-Engineered Tunneling Barriers,” which claims the priority of U.S. Provisional Application Ser. No. 61 / 163,883, filed Mar. 27, 2009 entitled “Resonant Tunneling Barrier Using C60 For Tunnel Oxide In Flash Memory,” which is incorporated herein by reference in its entirety.[0002]This application further relates to and derives priority from: (1) U.S. Provisional Patent Application Ser. No. 61 / 367,132, titled “Engineered Fullerene Molecules for Flash Memory Charge Storage,” and filed 23 Jul. 2010; and (2) U.S. Provisional Patent Application Ser. No. 61 / 367,144, titled “Engineered Fullerene Molecules (EFM) in Resonant Double Tunnel Structures for Non-Volatile Memory Applications,” and filed 23 Jul. 2010, the contents of which are incorporated herein...

AI Technical Summary

Benefits of technology

[0015]According to an aspect of the application, semiconductor devices can exhibit increased retention time / program-erase time ratios.

Problems solved by technology

However, this related art approach limits the scalability of the P / E voltage, which is quickly becoming the major scaling roadblock, considering power dissipation, cycling endurance, and peripheral circuitry design.

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