Method and apparatus for correcting phase offset errors in a communication device

Abstract

A frequency synthesizer that utilizes locked loop circuitry, for example delay locked loop and / or phase locked loop circuits is provided with a means for minimizing static phase / delay errors. An auto-tuning circuit and technique provide a measurement of static phase error by integrating the static phase error in the DLL / PLL circuit. A correction value is determined and applied as a current at the charge pump or as a time / phase offset at the phase detector to minimize static phase error. During normal operation the DLL / PLL is operated with the correction value resulting in substantially reduced spur levels and / or improved settling time.

Description

FIELD OF THE DISCLOSURE[0001]The present disclosure relates generally to electronic communication devices and more particularly to a method and apparatus for correcting static phase offset errors within the frequency synthesis operations of a communication device.BACKGROUND[0002]Communication products, such as two-way radios, cell phones, and the like, utilize frequency synthesizer circuits and frequency synthesis applications as a means of generating stable signals for use during transmit and receive modes of operation. Delay locked loop (DLL) circuits and phase locked loop (PLL) circuits typically form, either together or individually, a major part of the frequency synthesizer for any communication product. The DLL can be used in direct digital synthesis (DDS) applications while the PLL is typically utilized in more conventional frequency synthesis applications.[0003]The use of a DLL and DLL applications may incur static phase offset errors which can generate spurs in the output s...

AI Technical Summary

Problems solved by technology

The use of a DLL and DLL applications may incur static phase offset errors which can generate spurs in the output signal.

These spurs in the output signal are not desirable in a signal source that is used as a local oscillator in any transceiver system, as they might cause unwanted signals to appear along with the wanted signals.

These spurs adversely affect blocking performance (e.g. adjacent channel), self quieters, spectral mask capabilities and electro-magnetic interference (EMI) in transceiver systems.

Static phase offset errors inherent in these types of synthesizers are thus problematic.

The use of PLL and multiple loop PLL applications may incur static phase offset mismatch errors between loops which can create spurious glitches in a transient response that can negatively impact loop settling time.

Static phase offset errors inherent in these types of synthesizers are thus also problematic.

Therefore, adaptive-bandwidth DLL / PLL systems with large offset errors suffer from protracted settling times, negating much of the benefit of an adaptive-bandwidth scheme.

Additionally, the complexity and variation (across process, voltage, temperature) of current DLL and PLL and DLL / PLL systems burden users with expertise requirements, programming requirements and excessive system characterization requirements.

The causes of static errors include, for example, up / down mismatch errors in a phase frequency detector, charge pump currents and turn-on-times, and phase detector delays.

Without correcting or reducing the former error first, the latter error correction ends up being ineffective.

Any phase offset mismatch error between the NBW and WBW loop due to non-idealities of the phase detector, charge pump or any secondary effects will result in the measurement capacitor's 430 voltage ramping in either the positive or negative direction from VREF.

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