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Method and Apparatus for Performing Formal Verification of Polynomial Datapath

a polynomial data and verification method technology, applied in the direction of instruments, specific program execution arrangements, program control, etc., can solve the problems of formal verification, reducing the confidence gained from simulation alone, and giving absolute confiden

Active Publication Date: 2013-06-13
IMAGINATION TECH LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes a method and system for determining the functional equivalence of designs in RTL integrated circuit design. The method involves deriving a data flow graph representation of each design and comparing it to the original design to determine if they are functionally equivalent. The system includes a receiver for receiving a plurality of equivalent designs, a data flow graph derivation unit, and a comparator for comparing the modified designs. The technical effect of this patent is to extend the capabilities of current formal verification tools and techniques to more complex or larger designs by using polynomial datapath equivalence to provide equivalence of a range of designs.

Problems solved by technology

However, due to the ever increasing size of the input space, and the difficulty in resolving corner cases for complex designs, the confidence gained from simulation alone is becoming less and less sufficient.
Formal verification, on the other hand, gives absolute confidence but is limited in applicability to small or simple designs, due to the complexity of modelling and applying formal methods.
Commercially available tools such as Synopsys' Formality, www.synopsys.com / tools / verification / formalequivalence / pages / formality.aspx can formally prove equivalence between many designs but do not incorporate the theory of polynomial rings to simplify the verification of polynomial-like designs.
However, commercially available tools are frequently unable to prove equivalence of relatively trivial designs in a reasonable time period.
However, the power of formal verification tools is limited, meaning that designs over a certain size or complexity cannot be successfully verified against one another.
However, none of these formal methods are used in tandem with the input space reduction which arises from recognition of polynomial datapath.

Method used

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  • Method and Apparatus for Performing Formal Verification of Polynomial Datapath
  • Method and Apparatus for Performing Formal Verification of Polynomial Datapath

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0063]

t0[8:0]=c[7:0]+1

t1[15:0]=b[7:0]−t0

t2[15:0]=d[7:0]<

t3[15:0]=a[7:0]*t1

Y[15:0]=t3+t2   Design A

t0[8:0]=c[7:0]+1

t1[15:0]=d[7:0]<

t2[15:0]=a[7:0]*b[7:0]

t3[15:0]=a[7:0]*t0

Y[15:0]=t2−t3+t1+2*d[7:0]  Design B

t0[15:0]=c+1

t1[15:0]=b−t0

t2[15:0]=d<

t3[15:0]=a*t1

Y[15:0]=t3+t2   Design A′

t0[15:0]=c+1

t1[15:0]=d<<c

t2[15:0]=a*b

t3[15:0]=a*t0

Y[15:0]=t2−t3+t1+2*d   Design B′

[0064]The DFG of A′ can be found in FIG. 1. The strictly polynomial inputs are a, b and d. In this case n=16, so SF(216)=min(k:16≦k−Hamm(k))=18; λj=min(8,ceil(log2(SF(216))))=5

t0[15:0]=c[7:0]+1

t1[15:0]=b[4:0]−t0

t2[15:0]=d[4:0]<

t3[15:0]=a[4:0]*t1

Y[15:0]=t3+t2   Design A″

t0[15:0]=c[7:0]+1

t1[15:0]=d[4:0]<

t2[15:0]=a[4:0]*b[4:0]

t3[15:0]=a[4:0]*t0

Y[15:0]=t2−t3+t1+2*d[4:0]  Design B″

[0065]Formally verifying A″ against B″ is a much simpler verification than A against B.

[0066]Note that in general SF(2n) is of order n, thus reducing exponential complexity to linear complexity.

example 2

[0067]The following is a typical example in the context of an integer arithmetic logic unit.

t0[33:0]=a[1′5:0]*b[15:0]+c[15:0]t1[33:0]=-a[1′5:0]*b[15:0]+c[15:0]t2[33:0]=a[1′5:0]*b[15:0]-c[15:0]t3[33:0]=-a[1′5:0]*b[15:0]-c[15:0]t4[33:0]=a[1′5:0]*b[15:0]t5[33:0]=-a[1′5:0]*b[15:0]t6[33:0]=c[15:0]t7[33:0]=-c[15:0]DesignA:Y[33:0]=(s==0)?t0:(s==1)?t1:(s==2)?t2:(s==3)?t3:(s==4)?t4:(s==5)?t5:(s==6)?t6:t7DesignB:t0[33:0]=(s>5)?0:b[15:0]t1[33:0]=(s<4)?c[15:0]:(s[1]==1)?c[15:0]:0t3[33:0]=(s[2]⊕s[1]⊕s[0]==1)?t1_:t1t4[33:0]=a[15:0]*t0+t3+(s[2]⊕s[1]⊕s[0])-s[0]Y[33:0]=s[0]?t4_:t4DesignA′=DesignA:DesignB′=DesignBByapplyingAlgorithm1thestrictlypolynomialinputsarea,bandc.Inthiscasen=34,soSF(234)=min(k:34≤k-Hamm(k))=36λj=min(16,ceil(log2(SF(234))))=6

5 Polynomial Synthesis Via Formal Verification

[0068]The above methodology can improve or optimize verification of polynomial datapath design. In practical terms, when used in IC design verification can be implemented using standard synthesis tools. A ...

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Abstract

A method and apparatus are provided for use in synthesis of RTL integrated circuit design to determine the functional equivalence of designs. For example, the receiver receives a plurality of designs for synthesis in RTL and a data flow graph is derived for each design. Internal bit widths in the data flow graph representations are restricted (52) to provide a first modified version of each of the designs. These first modified versions are compared each with the design from which it was derived in a comparison unit (54). The input bit widths of the data flow graph representation are then restricted to be no wider than the output bit widths (56) to derive second modified versions of the designs (58). These second modified versions are compared with each other (60) to determine which are equivalent. Equivalent designs can be passed to an RTL synthesis unit 62, or otherwise further evaluated.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority from Great Britain Patent Application Number 1106055.5, filed on Apr. 8, 2011, entitled “Method and Apparatus for Performing the Synthesis of Polynomial Datapath via Formal Verification”, and which application is herein incorporated in its entirety herein for all purposes.BACKGROUND[0002]1. Field[0003]One aspect relates to methods and apparatus for use in the design and manufacture of integrated circuits, and in particular to methods and apparatus for confirming that two designs are functionally equivalent for a method of synthesis.[0004]2. Related Art[0005]The task of confirming that two designs are identical is one that is extremely important in all areas of hardware design. To replace an existing design in a portion of an integrated circuit with another which exhibits desirable synthesis properties, for example, first requires that a level of confidence that the two designs are functionally equivalent b...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F17/50
CPCG06F17/505G06F17/504G06F17/5081G06F17/5022G06F30/3323G06F30/398G06F30/327G06F30/33G06F2119/16G06F2119/18
Inventor DRANE, THEO ALANEXALL, FREDDIE RUPERT
Owner IMAGINATION TECH LTD
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