Reduction of oxide recesses for gate height control
a technology of oxide recesses and gate height control, which is applied in the direction of semiconductor devices, electrical equipment, transistors, etc., can solve the problems of excessive recesses, poor quality of gap filling, and prone to subsequent wet/dry etching processing
Inactive Publication Date: 2014-11-20
ALSEPHINA INNOVATIONS INC
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Benefits of technology
This approach effectively minimizes oxidation recesses and achieves uniform gate height by creating a planar surface overlaying the gate structures and sacrificial material, enhancing the reliability of semiconductor devices.
Problems solved by technology
However, the quality of the gap fill may typically be poor and may be vulnerable to subsequent wet / dry etch processing.
Subsequent chemical mechanical planarization of the tungsten and / or sacrificial nitride filler material may yield excessive recesses, particularly in the sacrificial material.
Method used
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[0020]Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and / or arrangements, within the spirit and / or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure.
[0021]Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic fun...
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An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.
Description
BACKGROUND OF THE INVENTION[0001]1. Technical Field[0002]The present invention generally relates to semiconductor devices and fabrication of the semiconductor devices. More particularly, the present invention relates to controlling gate height by reducing oxide recess and achieving gate height uniformity.[0003]2. Background Information[0004]Gate-first and Gate-last approaches have been two principle approaches for forming semiconductor device gate structures.[0005]In a gate-first fabrication approach, a metal gate is provided over a gate dielectric, and then patterned and etched to form one or more gate structures. After forming the gate structures, source and drain features of the semiconductor devices are provided. In the gate-last approach, a sacrificial(or dummy) gate material is provided, patterned and etched to define one or more sacrificial gates. The one or more sacrificial gates are subsequently replaced with corresponding replacement metal gates, such as, for example, amor...
Claims
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IPC IPC(8): H01L21/28H01L29/423H01L27/088
CPCH01L21/28008H01L29/4232H01L27/088H01L21/823437H01L21/28247H01L29/66545H01L29/4236H01L29/42364
Inventor CHEN, TSUNG-LIANGTAI, HSIN-NENGWANG, HUEY-MING
Owner ALSEPHINA INNOVATIONS INC