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Radiation tolerant dummy gate-assisted n-mosfet, and method and apparatus for modeling channel of semiconductor device

a technology of mosfet and gate-assisted n-mosfet, which is applied in the direction of semiconductor devices, electrical devices, basic electric elements, etc., can solve the problems of inability to solve the desired channel region geometry, leakage current induced, and blockage of the turn-off operation of the mos

Active Publication Date: 2015-01-01
KOREA ADVANCED INST OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0008]Another aspect of the present invention is to provide a method and apparatus for modeling a channel of a semiconductor device that can enhance semiconductor design efficiency by enabling rapid modeling of electrical characteristics of a unit semiconductor device when the channel geometry is varied according to design of the unit semiconductor device such as DGA MOSFET.
[0010]In a feature of the present invention, the dummy gate-assisted n-MOSFET (DGA n-MOSFET) layout can properly operate in a radioactive environment by blocking leakage current paths that may be created by radiation. Hence, the DGA n-MOSFET layout can be applied to design of electronic components operable in radioactive environments, such as outer space, planetary exploration, and in nuclear reactors in nuclear power plants.
[0011]In addition, when the geometry of a channel region becomes diverse due to practical extension thereof as in the case of radiation tolerant DGA n-MOSFETs whose channel region geometry is diverse, an analytical solution for the W / L ratio of the channel region may be not obtainable and hence the W / L ratio may have to be computed through simulation-based numerical analysis. The present invention proposes an effective W / L ratio model for approximating the W / L ratio in the above situation, thereby enabling practical circuit design using unit semiconductor devices having diverse channel region geometries such as radiation tolerant DGA n-MOSFETs.

Problems solved by technology

When a unit MOSFET (metal oxide semiconductor field effect transistor) is exposed to radiation for a long time, leakage current is induced and turn-off operation of the MOSFET may be blocked.
However, an analytical solution for a desired channel region geometry may not exist.
Designing and computing a channel region model with a specific geometry on a three-dimensional simulator may require a lot of time and effort.

Method used

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  • Radiation tolerant dummy gate-assisted n-mosfet, and method and apparatus for modeling channel of semiconductor device

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first embodiment

[0060]FIG. 5 shows a radiation tolerant DGA n-MOSFET layout according to the first embodiment of the present invention.

[0061]Referring to FIG. 5, in the first embodiment, the dummy poly gate layer 20, the dummy metal-1 layer 10, and the p-active layer and the p+ layer 30 are all used together as described before. In this case, each of these layers contributes to radiation tolerance, as described before. Particularly, at the p-active layer, the p+ layer 30 and the dummy metal-1 layer 10 may function to provide radiation resistance in an overlapping manner.

second embodiment

[0062]FIG. 6 shows a radiation tolerant DGA n-MOSFET layout according to the second embodiment of the present invention.

[0063]Referring to FIG. 6, in the second embodiment, only two layers of the dummy poly gate layer 20 and the dummy metal-1 layer 10 are used as described before. At the p-active layer, the dummy metal-1 layer 10 alone may function to impart radiation resistance. As the p+ layer and the dummy metal-1 layer 10 act on the same position, the dummy metal-1 layer 10 may be sufficient for radiation resistance as in the case of the second embodiment.

third embodiment

[0064]FIG. 7 shows a radiation tolerant DGA n-MOSFET layout according to the third embodiment of the present invention.

[0065]Referring to FIG. 7, in the third embodiment, only two layers of the dummy poly gate layer 20 and the p+ layer 30 are used as described before. At the p-active layer, the p+ layer 30 alone may function to impart radiation resistance. As the p+ layer 30 and the dummy metal-1 layer act on the same position, the p+ layer 30 may be sufficient for radiation resistance as in the case of the third embodiment.

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Abstract

The DGA n-MOSFET layout of the present invention can properly operate in a radioactive environment by blocking leakage current paths that may be created by radiation. Hence, the DGA n-MOSFET layout can be applied to design of electronic components operable in radioactive environments, such as outer space, planetary exploration, and in nuclear reactors in nuclear power plants. In addition, semiconductor design efficiency can be increased by enabling rapid modeling of electrical characteristics of a semiconductor device such as a DGA MOSFET when the channel region geometry is diversified according to design of the semiconductor device.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a radiation tolerant unit metal oxide semiconductor field effect transistor (MOSFET) and a method and apparatus for modeling a channel of a semiconductor device. More particularly, the present invention relates to a radiation tolerant dummy gate-assisted (DGA) unit MOSFET wherein the transistor layout of a unit MOSFET is modified so that the unit MOSFET is resistant to radiation, and to a method and apparatus for modeling a channel of a semiconductor device that can enhance semiconductor design efficiency by enabling rapid modeling of electrical characteristics of the channel region of a semiconductor device such as a DGA MOSFET when the channel geometry is varied according to design of the semiconductor device.[0003]2. Description of the Related Art[0004]When a unit MOSFET (metal oxide semiconductor field effect transistor) is exposed to radiation for a long time, leakage current is ind...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/78H01L29/423
CPCH01L29/78H01L29/4238H01L29/402H01L29/404H01L29/0638H01L29/0692H01L29/1033
Inventor LEE, HEE-CHULLEE, MIN-SU
Owner KOREA ADVANCED INST OF SCI & TECH
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