Microprocessor accelerated code optimizer

Inactive Publication Date: 2015-02-05
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention is a method for improving code optimization in a microprocessor. It involves fetching a sequence of instructions, decoding them into smaller instructions, and reordering them to create an optimized sequence for execution. This optimized sequence is then stored in a cache for later use. The technical effect of this invention is faster and more efficient code optimization, resulting in improved performance and efficiency of the microprocessor.

Problems solved by technology

However, this still has multiple draw backs, namely the area, power and complexity of duplicating all architecture state elements (i.e., registers) for each additional thread supported in hardware.
The hardware thread-aware architectures with duplicate context-state hardware storage do not help non-threaded software code and only reduces the number of context switches for software that is threaded.
However, those threads are usually constructed for coarse grain parallelism, and result in heavy software overhead for initiating and synchronizing, leaving fine grain parallelism, such as function calls and loops parallel execution, without efficient threading initiations / auto generation.
Such described overheads are accompanied with the difficulty of auto parallelization of such codes using sate of the art compiler or user parallelization techniques for non-explicitly / easily parallelized / threaded software codes.

Method used

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  • Microprocessor accelerated code optimizer
  • Microprocessor accelerated code optimizer
  • Microprocessor accelerated code optimizer

Examples

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Embodiment Construction

[0036]Although the present invention has been described in connection with one embodiment, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the scope of the invention as defined by the appended claims.

[0037]In the following detailed description, numerous specific details such as specific method orders, structures, elements, and connections have been set forth. It is to be understood however that these and other specific details need not be utilized to practice embodiments of the present invention. In other circumstances, well-known structures, elements, or connections have been omitted, or have not been described in particular detail in order to avoid unnecessarily obscuring this description.

[0038]References within the specification to “one embodiment” or “an embodiment” are intended to indicate that a particular feature, ...

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Abstract

A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The optimized microinstruction sequence is output to a microprocessor pipeline for execution. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This application is related to co-pending commonly assigned US Patent Application serial number 2010 / 0161948, titled “APPARATUS AND METHOD FOR PROCESSING COMPLEX INSTRUCTION FORMATS IN A MULTITHREADED ARCHITECTURE SUPPORTING VARIOUS CONTEXT SWITCH MODES AND VIRTUALIZATION SCHEMES” by Mohammad A. Abdallah, filed on Jan. 5, 2010, and which is incorporated herein in its entirety.[0002]This application is related to co-pending commonly assigned US Patent Application serial number 2009 / 0113170, titled “APPARATUS AND METHOD FOR PROCESSING AN INSTRUCTION MATRIX SPECIFYING PARALLEL IN DEPENDENT OPERATIONS” by Mohammad A. Abdallah, filed on Dec. 19, 2008, and which is incorporated herein in its entirety.[0003]This application is related to co-pending commonly assigned U.S. Patent Application Ser. No. 61 / 384,198, titled “SINGLE CYCLE MULTI-BRANCH PREDICTION INCLUDING SHADOW CACHE FOR EARLY FAR BRANCH PREDICTION” by Mohammad A. Abdallah, filed on Sep...

Claims

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Application Information

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IPC IPC(8): G06F9/38G06F9/30
CPCG06F9/30145G06F9/38G06F9/3838G06F9/3853G06F9/30174G06F9/3808G06F9/3887
InventorABDALLAH, MOHAMMAD
OwnerINTEL CORP