OpportunistIC placement of IC test strucutres and/or e-beam target pads in areas otherwise used for filler cells, tap cells, decap cells, scribe lines, and/or dummy fill, as well as product IC chips containing same

Abstract

Product ICs / wafers include additional diagnostic, test, or monitoring structures opportunistically placed in filler cell positions, within tap cells, within decap cells, within scribe line areas, and / or within dummy fill regions. Improved fabrication processes utilize data from such structure(s) in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of U.S. patent application Ser. No. 14 / 303,578, filed Jun. 12, 2014, which '578 application is a continuation-in-part of U.S. patent application Ser. No. 14 / 190,040, filed Feb. 25, 2014, which is a continuation-in-part of U.S. patent application Ser. No. 14 / 038,799, filed Sep. 27, 2013. This application also claims priority from the following Provisional U.S. Patent Applications: Ser. No. 61 / 942,163, filed Feb. 20, 2014; Ser. No. 61 / 971,306, filed Mar. 27, 2014; Ser. No. 61 / 972,787, filed Mar. 31, 2014; Ser. No. 61 / 982,652, filed Apr. 22, 2014; and Ser. No. 62 / 011,161, filed Mar. 12, 2014. Each of the '578, '040, '799, '163, '306, '787, '652 and '161 applications is incorporated by reference herein.FIELD OF THE INVENTION[0002]This invention relates to the field of semiconductor integrated circuits and to methods for manufacturing and testing such circuits.BACKGROUND OF THE INVENTION[0003]Placement of “te...

AI Technical Summary

Benefits of technology

The present invention provides techniques for improving test structure coverage on product ICs with little or no sacrifice of active die area. This is achieved by replacing non-functional cells with self-contained test structures that require no additional interconnect. The invention also includes opportunistically inserting test pads into empty spaces within the IC layout, such as filler, decap, and tap cells, to improve test coverage without affecting the performance of the product. The invention also provides methods for designing and manufacturing ICs with these improved test structures. Overall, the invention allows for better test structure coverage without sacrificing active die area, and improves the efficiency and accuracy of IC design and manufacturing.

Problems solved by technology

While these and other known techniques that locate test structures on product wafers produce useful results, they are still less than ideal.

Specifically, the area available in the scribe line of product wafers is strictly limited and can only accommodate certain types of test structures.

Additionally, both the in-the-scribe-line and under-the-probe-pad methods suffer from the fact that the test structures are located far away from the most important active circuitry regions, and are thus not likely to accurately represent the processing environment of the active circuitry.

Although the '083 patent can potentially mitigate this problem, it does so at the unacceptable cost of requiring large, dedicated test regions (see '083 patent, FIG. 5, regions 44-45) that consume otherwise precious active die area.

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