Material processing to achieve sub-10nm patterning

a material processing and sub-10nm technology, applied in the direction of electrical equipment, basic electric elements, electric discharge tubes, etc., can solve the problems of inconvenient methods and spatial limitations inherent in the conventional dp technique, and achieve the effect of increasing the pattern density of the structur

Active Publication Date: 2016-08-25
TOKYO ELECTRON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

There are some spatial limitations inherent in the conventional DP technique due to deposition ‘thin-ness’ limitations and pitch of the features from mandrel formation limitations.
These methods can become costly and add several steps to the process.
Advanced extreme ultra violet (EUV) lithography should be able to alleviate some of these issues once available but the constant drive to smaller CD will remain a challenge for the future technologies to come.

Method used

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  • Material processing to achieve sub-10nm patterning
  • Material processing to achieve sub-10nm patterning
  • Material processing to achieve sub-10nm patterning

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Embodiment Construction

[0040]In the following description, for purposes of explanation and not limitation, specific details are set forth, such as a particular geometry of a processing system, descriptions of various components and processes used therein. However, it should be understood that the invention may be practiced in other embodiments that depart from these specific details.

[0041]Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0042]Various operations will be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations...

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Abstract

Provided is a method for increasing pattern density on a substrate comprising a structure with a patterned layer with a first composition and a sidewall and a cap layer of a second composition formed atop said structure. The sidewall is exposed to a chemical environment and creates a chemically modified sidewall layer of a third composition. The cap layer and an interior, non-modified portion of said structure is removed using an etching process to leave behind said chemically modified sidewall layer. A pattern transfer etch of said sidewall chemically modified layer onto the underlying layer of said substrate is performed. One or more integration operating variables are controlled to achieve target critical dimensions comprising width, height, sidewall angle, line width roughness, and / or line edge roughness of said structure.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of Invention[0002]The invention relates to a method of performing a sequence of semiconductor patterning operations on a substrate and specifically to perform patterning of a structure on the substrate under 10 nm.[0003]2. Description of Related Art[0004]In semiconductor manufacturing patterning of a film on a substrate can be achieved through several methods that have evolved with time to follow Moore's law. The first method is conventional lithography which can no longer be used alone to achieve advanced nodes critical dimensions (CD).[0005]Double patterning is the technique used to create hard mask features smaller than photolithographic capabilities by using spacer deposition to define feature dimensions. Typical double patterning (DP) techniques require a sequence of deposition over a mandrel, etch to form the spacer and another etch to remove the mandrel, with both deposition and etch tools required. There are some spatial limitations ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/033H01L21/311
CPCH01L21/0338H01L21/823431H01L21/31116H01L21/31144H01J37/32082H01J37/32192H01L21/0337H01L21/32105H01L21/32139
Inventor O'MEARA, DAVID L.RALEY, ANGELIQUE D.KO, AKITERUITO, KIYOHITO
Owner TOKYO ELECTRON LTD
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