Assessment of a High Performance Computing Application in Relation to Network Latency Due to the Chosen Interconnects

a high-performance computing and network latency technology, applied in the field of high-performance computing, can solve the problems of prohibitively high cost and latency in the transmission of instructions, and achieve the effect of adding delay and therefore latency

Inactive Publication Date: 2017-02-02
SILICON GRAPHICS INT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

Enables cost-effective simulation of different interconnects within HPC systems, providing insights into performance impacts without physical component replacement, facilitating informed purchasing decisions and performance optimization.

Problems solved by technology

Given the complexity and size of such systems, testing often occurs through simulation or testing of selected groupings of components.
A change to a slower switching fabric may result in latency in the transmission of instructions.
However, this is prohibitively expensive.

Method used

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  • Assessment of a High Performance Computing Application in Relation to Network Latency Due to the Chosen Interconnects
  • Assessment of a High Performance Computing Application in Relation to Network Latency Due to the Chosen Interconnects
  • Assessment of a High Performance Computing Application in Relation to Network Latency Due to the Chosen Interconnects

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Embodiment Construction

[0006]In a first embodiment of the invention there is provided a method for testing a high performance computing application performing a computation within a high performance computing arrangement. An application includes multiple processes working in conjunction to complete the calculation. Often processes are mapped to processor cores in a one-to-one or a one-to-many configuration. The high performance computing arrangement performs computations across processors in parallel wherein processes cooperate to perform the computation using the processors. The application can be tested using a performance-profiling tool that can add delay and therefore latency to one or more commands inside of the precompiled application. The addition of delay can be used to simulate the performance of different interconnects that are used within the clustered computing arrangement.

[0007]First, a performance-profiling tool is executed on the clustered computer arrangement having an associated first int...

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Abstract

A method and computer program product for testing a high performance computing application performing a computation within a clustered computer arrangement is disclosed. The high performance computing arrangement performances computations across processors in parallel wherein the processors cooperate to perform the computation. The application can be tested by adding delay and therefore latency to one or more commands inside of the precompiled application. The addition of delay can be used to simulate the performance of different interconnects that are used within the high performance computing arrangement.

Description

TECHNICAL FIELD[0001]This application is a continuation application of Ser. No. 13 / 928,050 filed on Jun. 26, 2013. The present invention relates to high performance computing, and more particularly to introducing latency into commands in a compiled application during runtime to simulate different interconnects between nodes and switches.BACKGROUND ART[0002]High performance computing (“HPC”) systems perform complex or data-intensive calculations using a large number of computing nodes. For example, some HPC systems may be used to multiply matrices that have thousands or even hundreds of thousands of rows and form outer products of vectors having hundreds of thousands of elements. HPC software developers break up such problems into smaller problems that may be executed with relative independence. For example, in a matrix multiplication C=A*B, calculating the value of an element in the matrix C requires as input only a single row of the matrix A and a single column of the matrix B. Thu...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G06F11/30G06F11/34G06F17/50G06F11/36
CPCG06F11/3006G06F11/3668G06F11/3404G06F17/5009G06F11/3428G06F11/3447G06F11/3457G06F11/3419G06F11/3461G06F11/3466G06F30/20
InventorTHOMAS, DANIELBARON, JOHN E.
OwnerSILICON GRAPHICS INT CORP