Hardware-based run-time mitigation of blocks having multiple conditional branches

a conditional branch and run-time mitigation technology, applied in the field of processor design, can solve problems such as significant degradation of latency and efficiency

Inactive Publication Date: 2017-05-04
CENTIPEDE SEMI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0021]There is further provided, in accordance with an embodiment of the present invention, a processor including an instruction pipeline and circuitry. The instruction pipeline is configured to process a sequence of pre-compiled instructions. The circuitry is configured to identify in the instructions flowing via the pipeline a first block of instructions, which includes at least first and second conditional branch instructions that conditionally diverge execution of the inst

Problems solved by technology

While highly-accurate branch prediction can boost the processor performance considera

Method used

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  • Hardware-based run-time mitigation of blocks having multiple conditional branches
  • Hardware-based run-time mitigation of blocks having multiple conditional branches
  • Hardware-based run-time mitigation of blocks having multiple conditional branches

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Embodiment Construction

Overview

[0030]Embodiments of the present invention that are described herein provide improved methods and devices for reducing the performance degradation caused by branch misprediction. In the disclosed embodiments, a processor comprises an instruction pipeline that processes pre-compiled program code. The processor monitors the instructions that flow through its pipeline and identifies, at runtime, one or more “conditional blocks” of instructions. A conditional block comprises a conditional branch instruction that diverges the execution flow into at least first and second flow-control traces. The first and second traces differ from one another in multiple instructions, and then converge at a given instruction that is again common to the first and second flow-control traces.

[0031]The conditional branch instruction is typically located at the beginning of the conditional block. In some cases the conditional branch instruction is a forward branch. In other cases, the conditional bran...

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Abstract

A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes at least first and second conditional branch instructions that conditionally diverge execution of the instructions into a plurality of flow-control traces that differ from one another in multiple instructions and converge at a given instruction. A second block of instructions, which is logically equivalent to the first block but replaces the plurality of flow-control traces by a reduced set of one or more flow-control traces, having fewer flow-control traces than the first block, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Patent Application 62 / 249,278, filed Nov. 1, 2015. This application is related to a U.S. Patent Application entitled “Hardware-based run-time mitigation of conditional branches,” Attorney docket number 1279-1013.1, filed on even date. The disclosures of these related applications are incorporated herein by reference.FIELD OF THE INVENTION[0002]The present invention relates generally to processor design, and particularly to methods and systems for run-time processing of conditional instruction blocks.BACKGROUND OF THE INVENTION[0003]Most modern processors use branch prediction mechanisms to improve performance. While highly-accurate branch prediction can boost the processor performance considerably, branch misprediction may cause significant degradation in latency and efficiency.[0004]Various techniques have been suggested for improving the performance of branch prediction, or to redu...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/38
CPCG06F9/3867G06F9/30058G06F9/30072G06F9/3808G06F9/3844G06F9/3858G06F8/443G06F9/30079G06F9/30065G06F9/30061G06F9/45516G06F9/3842
Inventor FRIEDMANN, JONATHANGOREN, IDOKOREN, SHAYMIZRAHI, NOAMMANDLER, ALBERTO
Owner CENTIPEDE SEMI
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