Vertical SRAM structure

Abstract

A vertical SRAM cell includes a first (1st) inverter having a 1st pull-up (PU) transistor and a 1st pull-down (PD) transistor. The 1st PU and 1st PD transistors have a bottom source / drain (S / D) region disposed on a substrate and a channel extending upwards from a top surface of the bottom S / D region. A second (2nd) inverter has a 2nd PU transistor and a 2nd PD transistor. The 2nd PU and 2nd PD transistors have a bottom S / D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S / D region. A 1st metal contact is disposed on sidewalls, and not on the top surface, of the bottom S / D regions of the 1st PU and 1st PD transistors. A 2nd metal contact is disposed on sidewalls, and not on the top surface, of the bottom S / D regions of the 2nd PU and 2nd PD transistors.

Description

TECHNICAL FIELD[0001]The present invention relates to semiconductor devices and methods of making the same. More specifically, the invention relates to vertical Static Random Access Memory (SRAM) cell structures and methods of making the same.BACKGROUND[0002]SRAM cells (or SRAM cell structures) in general are random access memory cells that retain data bits in their memory as long as power is being supplied. SRAM is used in personal computers, workstations, routers, peripheral equipment and the like.[0003]SRAM cells are composed of a pair of cross coupled inverters connected together to form dual (first and second) storage node outputs with opposing logic states. Therefore SRAM cells have two stable logic states. The first logic state includes a logic one (1) and a logic zero (0) at the first and second storage node outputs, respectively. The second state includes a logic 0 and a logic 1 at the same first and second storage node outputs, respectively.[0004]The storage nodes will be ...

AI Technical Summary

Benefits of technology

This approach enhances the reliability of electrical continuity for metal contacts and prevents contamination of channels, addressing the challenges of downsizing in vertical SRAM cells by maintaining performance and reducing the risk of electrical shorts.

Problems solved by technology

SRAM cells are constantly being down-sized to meet increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits in semiconductor structures.

However, such down-sizing provides technical challenges that become increasingly problematic, especially for horizontal SRAM cells.

Moreover, it becomes ever more difficult to increase the overall area (or footprint) along the substrate plane of a semiconductor structure to accommodate larger numbers of horizontal SRAM cells as complexity of the semiconductor structure increases.

However, landing metal contacts on the bottom S / D regions of vertical FinFETs becomes increasingly difficult as the vertical SRAM cells are downsized.

Moreover, the metal contacts of prior art vertical FinFETs can get unacceptably close to the vertical channels when connecting to the bottom S / D regions.

If the metal contacts touch the vertical channels, the metal contacts can contaminate the channel and adversely affect performance.

Such cross-coupled contacts are subject to similar types of technical problems as that of the placing of the metal contacts within a vertical SRAM cell.

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