Isolated power transfer with integrated transformer and voltage control

[0021]The use of the same reference symbols in different drawings indicates similar or identical items.

DETAILED DESCRIPTION

[0022]A low-cost, power transfer device includes a transformer formed on an insulating substrate disposed on conductive structures within an integrated circuit package. A primary winding of the transformer is coupled to a first integrated circuit to form a DC/AC power converter and a secondary winding of the transformer is coupled to a second integrated circuit to form an AC/DC power converter. The first and second integrated circuits are electrically isolated from each other, i.e., no current flows between the first and second integrated circuits.

[0023]Power transfer device 200 includes DC/AC power converter circuit 202, which uses input DC signal VDD1 to bias conductive coil 206 of transformer 209, and AC/DC power converter circuit 204, which uses conductive coil 208 of transformer 209 to drive capacitor C1. In at least one embodiment, an oscillator circuit includes conductive coil 206 and DC/AC power converter circuit 202 to form a fast-starting oscillator stage configured to operate as a Class-D power amplifier that is configured as a primary-side power converter stage. This primary-side power converter stage may be tuned to oscillate with a particular frequency, e.g., approximately 60 MHz-400 MHz, using variable capacitors. Power transfer device 200 regulates output voltage VDD2 by turning on and off DC/AC power converter circuit 202 using feedback information received from feedback circuit 210 via capacitive channel 220 to communicatively couple electrically isolated integrated circuits. Capacitive channel 220 communicates the feedback information across an isolation barrier from the primary side to the secondary side. The feedback may be provided as a digital signal communicated across the isolation barrier using transmitter 216 and receiver 214 that implement on-off keying (OOK) modulation of the information transmitted across the capacitive channel 220.

[0024]In at least one embodiment, the primary-side power converter stage formed by conductive coil 206 and the oscillator in DC/AC power converter circuit 202 operates as a high-efficiency Class-D power amplifier. Class-D operation may cause a pseudo-differential signal on nodes TX+ and TX− to have peak voltage levels (e.g., 15 V) up to, or slightly greater than, 3.2×VDD1. Such voltage levels are not tolerated by conventional CMOS devices (e.g., conventional CMOS transistors operate up to 1.2×VDD1). Conventional oscillator circuit 302 of FIG. 3, which includes a latch circuit formed from conventional n-type transistor 306 and n-type transistor 308, is inadequate to support the high gate-to-source voltage levels and drain-to-source voltage levels of the target specifications for the primary-side power converter stage.

[0025]Referring to FIG. 4, in at least one embodiment, oscillator circuit 402 includes a latch circuit formed by latch transistor 408 and latch transistor 410, which are n-type transistors cross-coupled to each other and coupled to cascode transistor 404 and cascode transistor 406, which are also n-type transistors. Latch transistor 408 and latch transistor 410 are on the primary side (e.g., low voltage side) of the power transfer device and are configured to pump energy into the LC tank circuit of oscillator circuit 402 at a frequency that is determined by passive system elements. Conductive coil 206 (i.e., the primary-side winding of transformer 209) can experience voltages as high as 3×VDD1 due to the Class-D mode operation (e.g., the pseudo-differential signal on nodes VHa and VHb having voltage levels in a range between 2.6×VDD1 and 3.2×VDD1) of oscillator circuit 402. Oscillator circuit 402 is selectively enabled via cascode transistors 404 and 406, which can cut off the current path to transformer 209. The Class-D operation of oscillator circuit 402 reduces transition times between the on (i.e., conducting) portion of oscillator circuit 402 and the off (i.e., non-conducting) portion of oscillator circuit 402, which realizes near-instant- or near-zero voltage switching in the primary-side power converter stage, thereby increasing efficiency by limiting the time duration in which both n-type transistors consume power and reducing or eliminating overshoots or undesired transients in the delivery of energy to the secondary-side power converter stage.

[0026]In at least one embodiment of oscillator circuit 402, cascode transistor 404 and cascode transistor 406 are laterally-diffused drain metal oxide semiconductor (LDMOS) transistors engineered for a high breakdown voltage. An exemplary LDMOS transistor can sustain high drain-to-source voltages (e.g., tens of Volts) while having low equivalent on-resistances (Rdson) in response to being driven into the linear mode of transistor operation. In at least one embodiment of the power transfer device, transistor 404 and transistor 406 are 18 V LDMOS n-type transistors, which are available in an exemplary manufacturing process for mixed-signal integrated circuits (e.g., a bipolar-CMOS-DMOS manufacturing process). Other transistors used by oscillator circuit 402 (e.g., latch transistor 408 and latch transistor 410) are conventional 5 V CMOS devices that have a breakdown voltage that is just over VDD1 (e.g., a breakdown voltage in a range greater than 5 V, but less than 6 V). Cascode transistor 404 and cascode transistor 406 shield the latch circuit from high voltages. The drain terminals of cascode transistor 404 and cascode transistor 406 can support high drain-to-source voltage swings while corresponding gate-to-source voltages are maintained within reliability limits determined by gate oxide thicknesses of the transistors (e.g., Vgs<6 V).

[0027]For a voltage level of input DC signal VDD1 equal to 5 V, drains of cascode transistor 404 and cascode transistor 406 will see voltages slightly higher than 3×VDD1=15 V. Cascode transistor 404 and cascode transistor 406 enable fast restart of the oscillator by presenting a sudden large voltage (e.g., a voltage above the latch crossover point, i.e., the point at which the gate-to-source voltage of latch transistor 410 equals the gate-to-source voltage of latch transistor 408) across latch transistor 408 and latch transistor 410. Voltages applied to latch transistor 408 and latch transistor 410 are precisely controlled so that those transistors enter the triode mode of operation and turn off at an appropriate time with little or no crossover time (i.e., the transition time when latch transistor 408 and latch transistor 410 are conducting in the active mode of operation). Each of latch transistor 408 and latch transistor 410 conducts during approximately one half of the cycle and does not conduct during the other half of the cycle. The capacitor of oscillator circuit 402 can be fully differential (Cp), single-ended (Cpa and Cpb) or a combination of fully differential and single-ended. Every 2C units of capacitance on each single-ended branch is equivalent to C fully differential units. The total equivalent capacitance seen by the oscillator circuit is Cp Cp(a,b)/2.

[0028]Referring to FIG. 5, in at least one embodiment, oscillator circuit 402 includes clamp transistor 412 and clamp transistor 414 coupled to the gate terminal of latch transistor 410 and the gate terminal of latch transistor 408, respectively. Clamp transistor 412 and clamp transistor 414 limit the gate-to-source voltages of latch transistor 408 and latch transistor 410, respectively, to a maximum of approximately VDD1+|Vtp|. Clamp transistor 412 and clamp transistor 414 are p-type transistors configured to suppress any substantial coupling across the drain-to-source parasitic overlap capacitance of cascode transistor 404 and cascode transistor 406, respectively, if cascode transistor 404 and cascode transistor 406 try to lift the gate-to-source voltages of latch transistor 408 and latch transistor 410, respectively, above VDD1+|Vtp|. For an exemplary 5 V CMOS process, VDD1 is 5 V and |Vtp| is approximately 1 V, and the clamping occurs at approximately 6 V, which is close to the maximum gate-to-source voltage that a conventional 5 V transistor can withstand.

[0029]Referring to FIG. 6, in at least one embodiment, oscillator circuit 402 includes clamp transistor 416 and clamp transistor 418 having source terminals coupled to the gate terminal of latch transistor 410 and the gate terminal of latch transistor 408, respectively. Clamp transistor 416 and clamp transistor 418 each include a bulk terminal, a gate terminal, and a drain terminal that are coupled to the power supply node providing input DC signal VDD1. Note that clamp transistor 416 and clamp transistor 418 are p-type transistors that have their n-type bulk terminal coupled to a corresponding drain node and not to a corresponding source node (i.e., a higher voltage node), as in typical clamp transistor configurations. The configuration of clamp transistor 416 and clamp transistor 418 results in two conduction paths for each clamp transistor: a channel conduction path and a body diode conduction path. Two conduction paths for each clamp transistor makes this configuration faster than the typical clamp transistor configuration. Clamp transistor 416 and clamp transistor 418 limit the voltages of node VLa and node VLb. If the voltages on node VLa or node VLb exceeds VDD1, then both the channel diode and the body diode of clamp transistor 416 and clamp transistor 418 start conducting, thereby clamping the gate voltages of latch transistor 410 and latch transistor 408. Clamp transistor 416 and clamp transistor 418 are configured to return part of the clamped energy back to the power supply, thereby increasing the efficiency of oscillator circuit 402.

[0030]The enable mechanism for controlling oscillator circuit 402 needs a mechanism that reduces or eliminates excess energy that builds up in the transformer coils upon restart and that can cause flying voltages on the terminals of the transformer (i.e., voltage levels much greater than 3×VDD1 that develop on either node VHa or node VHb as a result of releasing that excess energy to the capacitor(s) of the oscillator (e.g., Cp, Cpa, Cpb) as the oscillator restarts oscillating). Referring to FIGS. 7-9, embodiments of oscillator circuit 402 include snubber circuit 420 and snubber circuit 422 coupled to the drain terminal of cascode transistor 404 and the drain terminal of cascode transistor 406, respectively. Snubber circuit 420 and snubber circuit 422 prevent the voltage on the drain terminal of cascode transistor 404 and the voltage on the drain terminal of cascode transistor 406, respectively, from substantially exceeding 3×VDD1. As a result, snubber circuit 420 and snubber circuit 422 reduce or eliminate any non-fundamental modes of oscillation (i.e., modes of oscillation with an effective oscillation frequency other than

f = 1 2 π LC )

and force clean, well-bounded oscillation of oscillator circuit 402. In addition, snubber circuit 420 and snubber circuit 422 return at least part of the excess energy to the power supply. Snubber circuit 420 and snubber circuit 422 may be sized to have a clamping voltage level just above 3×VDD1. In at least one embodiment of oscillator circuit 402, snubber circuit 420 and snubber circuit 422 each include series-coupled, reverse-biased Zener diodes coupled in series with series-coupled, forward-biased diodes. Accordingly, the clamping voltage level equals N1×VZ+N2×VF, where N1 and N2 are integers greater than zero, VZ is a knee voltage of the Zener diodes, and VF is a forward voltage of the forward-biased diodes. Referring to FIG. 10, waveforms for oscillator circuit 402 illustrate pseudo-differential signals on nodes VHb and VHa, with peak voltages slightly higher than 3×VDD1.

[0031]Referring to FIG. 2, oscillator circuit 202 converts input DC signal VDD1 to an AC signal (e.g., the pseudo-differential signal on nodes TX+ and TX−). Transformer 209 converts that AC signal into a second AC signal (e.g., the pseudo-differential signal on nodes RX+ and RX−). AC/DC power converter circuit 204 receives the second AC signal from conductive coil 208 and converts the second AC signal (e.g., the pseudo-differential signal on nodes RX+ and RX−) into output DC signal VDD2 that is electrically isolated from the input DC signal VDD1. AC/DC power converter circuit 204 includes a full-wave rectifier circuit. Referring to FIGS. 2 and 12, in at least one embodiment, to improve the efficiency of power transfer device 200 as compared to efficiency realized by conventional power transfer devices, conductive coil 208 includes a center tap coupled to a ground node and rectifier circuit 403 includes Schottky diode 1202 and Schottky diode 1204.

[0032]In general, a Schottky diode (i.e., hot carrier diode) is a semiconductor diode formed by a junction of a semiconductor with a metal and is characterized to have a fast switching speed and low voltage drop. The Schottky diode can sustain high forward currents at lower voltage drops than would exist in typical diffused pn-junction diodes. An exemplary Schottky diode forward voltage is approximately 150 mV-450 mV, while a typical silicon diode has a forward voltage of approximately 600 mV-700 mV. The lower forward voltage requirement improves system efficiency. Typically, Schottky diodes are not available in conventional CMOS manufacturing technologies because their manufacture requires additional mask layers and processing steps. However, Schottky diodes may be available with conventional CMOS devices in an exemplary mixed-signal integrated circuit manufacturing process (e.g., bipolar-CMOS-DMOS manufacturing process). Schottky diode 1202 and Schottky diode 1204 withstand voltages of greater than 10 V in a typical application. The secondary-side half-windings alternate rectifying and adding charge to capacitor C1. Since only half of the transformer delivers power to the output capacitor for a particular half-cycle, the output voltage that can be developed across C1 is limited. However, only one Schottky diode contributes to conduction losses according to which path is conducting at a particular time. Schottky diodes that have high current density and relatively low reverse breakdown voltage may be used to reduce area of the rectifier circuit. If Schottky diodes are not available, regular diodes may be used, but result in a lossier system.

[0033]Referring to FIG. 13, in at least one embodiment of a power transfer device, rectifier circuit 403 includes conductive coil 208 with an unconnected center tap. Instead of a two-diode rectification structure, rectifier circuit 403 includes a four-diode rectification structure. Diode 1204, diode 1206, diode 1208, and diode 1210 are Schottky diodes, but regular diodes, which have higher losses across the diode, may be used. The embodiment of FIG. 13 allows a larger range of output voltage levels for output DC signal VDD2 since the entirety of conductive coil 208 delivers energy to the load during each half-cycle, as compared to the embodiment of FIG. 12. However, the embodiment of FIG. 13 has increased conduction losses because the average output load current conducts across two diodes and incurs two diode forward-voltage drops, instead of one diode forward-voltage drop of the embodiment of FIG. 12.

[0034]Replacing diode 1208 and diode 1210 of the embodiment of FIG. 13 with transistors 1212 and 1214 of FIG. 14, improves efficiency of rectifier circuit 403 by reducing conduction losses and the voltage drop across transistor 1212 and transistor 1214 can be made lower than the forward voltage drop of the Schottky diodes, as compared to the embodiment of FIG. 13. Referring to FIG. 14, in at least one embodiment, rectifier circuit 403 includes Schottky diode 1202 and Schottky diode 1204 integrated with conventional CMOS devices (e.g., cross-coupled n-type transistor 1212 and n-type transistor 1214). Conductive coil 208 is not coupled at a center tap. Regulating the output voltage level at an output DC signal VDD2 such that VDD2+VF falls below the maximum gate-to-source voltage of transistor 1212 and transistor 1214 alleviates reliability concerns related to the maximum gate-to-source voltage of transistor 1212 and transistor 1214. When either of transistor 1212 or transistor 1214 of FIG. 14 conducts (e.g., the path through transistor 1214, conductive coil 208, and diode 1202 or the path through transistor 1212, conductive coil 208, and diode 1204), both the channel and the body diode of transistor 1212 conduct, thus reducing conduction losses as compared to the four-diode embodiment of FIG. 13. Referring to FIGS. 14 and 15, waveform 1502 illustrates conduction through transistor 1212, conductive coil 208, and diode 1204 and waveform 1504 illustrates conduction through transistor 1214, conductive coil 208, and diode 1202. Waveform 1506 illustrates the rectified DC voltage (5 V) developed as the output DC signal VDD2 across capacitor C1.

[0035]Referring to FIG. 16, power transfer device 1600 includes oscillator circuit 402 coupled to conductive coil 206, and is configured to deliver energy from a first voltage domain across an isolation barrier via transformer 209, which delivers power to a second voltage domain of load 1650 via second conductive coil 208 and rectifier circuit 403. Typically, load 1650 and capacitor C1 are external to a package housing power transfer device 1600. Oscillator circuit 402 is controlled with an enable/disable signal that controls the amount of energy delivered to the secondary side of transformer 209, thereby regulating output DC signal VDD2. Referring to FIGS. 16 and 17, power transfer device 1600 isolates the first voltage domain on the primary side from the second voltage domain on the secondary side and allows data transfer between the primary side and the secondary side. No external DC-to-DC converter is necessary to power up the second voltage domain. Transformer 209 is an air core transformer that is integrated in package 1702 (e.g., a wide body small outline integrated circuit (WBSOIC) package). Integration of transformer 209 in power transfer device 1600 reduces bill of material costs and board space requirements of a voltage isolation system in an intended application (e.g., industrial and automotive applications).

[0036]FIGS. 17 and 18 illustrate a plan view of package 1702 housing power transfer device 1600 and transformer 209 and a cross-sectional view of cross-section 1800 of transformer 209 disposed on conductors in package 1702. In at least one embodiment, transformer 209 is an air core transformer with a 1:N turns ratio, where N can be approximately one. Each conductive coil of transformer 209 includes two turns each, and has a planar spiral structure. However, one of skill in the art will appreciate that the teachings herein can be utilized with other transformers using other turn ratios and/or other numbers of turns per coil. Transformer 209 converts the AC electrical energy on the primary side into magnetic flux, which is coupled into the secondary side of power transfer device 1600. Transferring energy from the primary side to the secondary side requires reinforced isolation, i.e., the primary and secondary sides of transformer 209 need to be able to withstand voltage surges greater than 5 kV RMS. Accordingly, the material used in the core of the transformer that isolates conductive coil 206 from conductive coil 208 needs to be able to withstand voltage surges greater than 5 kV RMS. Transformer 209 has a physical design and is formed using materials that reduce series resistance of conductive coil 206 and conductive coil 208 and improve the quality factor of the transformer 209, which increases the efficiency of transformer 209.

[0037]In at least one embodiment, package 1702 houses power transfer device 1600 and transformer 209 is formed using insulating substrate 1802. Insulating substrate 1802 is a glass substrate having a high transition temperature (i.e., a high Tg, e.g., Tg of at least approximately 150 C) and a low dielectric constant (e.g., borosilicate glass, e.g., Tg of approximately 150), a resin-based substrate (e.g., Bismaleimide-Triazine (BT)), or a glass-reinforced epoxy laminate (FR-4). By forming transformer 209 on insulating substrate 1802, transformer 209 can be disposed directly on conductor 1705, conductor 1706, conductor 1707, and conductor 1708, which may be formed from plated copper or other conductor within package 1702. Although insulating substrate 1802 is physically in contact with conductor 1705, conductor 1706, conductor 1707, and conductor 1708, transformer 209 is electrically isolated from conductor 1705, conductor 1706, conductor 1707, and conductor 1708, thereby reducing physical size requirements for a package housing transformer 209 in conjunction with other integrated circuits of power transfer device 1600. For example, integrated circuit 1710 includes oscillator circuit 402, integrated circuit 1712 includes rectifier circuit 403, integrated circuit 1718 includes feedback and fault tolerance circuitry, integrated circuit 1714 includes communication channel receiver circuitry, and integrated circuit 1716 includes communication channel transmitter circuitry. However, in at least one embodiment of power transfer device 1600, circuits of integrated circuit 1712, integrated circuit 1716, and integrated circuit 1718 (e.g., rectifier circuit 403, feedback and fault tolerant circuitry, and isolation channel transmitter circuitry) are integrated in fewer integrated circuit die or a single integrated circuit die that are/is coupled to transformer device 1704. Similarly, in at least one embodiment of power transfer device 1600, circuits of integrated circuit 1710 and integrated circuit 1714 (e.g., oscillator circuit 402 and communication channel receiver circuitry) are integrated in a single integrated circuit die that is coupled to transformer device 1704.

[0038]Integrated circuit 1710 and integrated circuit 1712 are coupled to transformer device 1704 using wire bonding or other integrated circuit interconnect. In at least one embodiment, first conductive coil 206 is formed from a conductive layer followed by conventional photolithographic patterning. For example, a conductive layer (e.g., a copper layer) is formed on insulating substrate 1802. A photoresist is applied and a reticle including a pattern for first conductive coil 206 is used to selectively expose the photoresist material. The manufacturing process removes unwanted material (e.g., unwanted material is etched away). Instead of a subtractive patterning process, an additive patterning process may be used to form conductive structures only in regions that need the material. Insulating layer 1804 is formed on first conductive coil 206. Then, second conductive coil 208 and interconnection structures (not shown) are formed on insulating layer 1804. Insulating layer 1804 may be any low dielectric constant material having a high dielectric strength (e.g., epoxy-based photoresist, high temperature polyimides, silicon dioxide or other thin film material having a dielectric constant of less than 10). Thus, conductive coil 206 and conductive coil 208 are formed in different layers on insulating substrate 1802. Transformer 209 may include ground pins to increase heat dissipation and reduce junction temperature rise. Transformer 209 may include two-turn conductive coils that have dimensions that reduce electromagnetic interference (e.g., symmetrical coils with current flow in opposing directions) and achieve sufficient efficiency.

[0039]Referring to FIGS. 16 and 17, feedback circuit 1608 is a hysteretic circuit that regulates output DC signal VDD2 based on voltage VSNS on a terminal SNS, which is a voltage-divided version of output DC signal VDD2 generated by a resistor divider network. Hysteresis is used to generate a feedback signal that controls oscillator circuit 402 to maintain the output voltage level of output DC signal VDD2 within a target voltage range. In an exemplary embodiment of power transfer device 1600, VDD2,MAX is 5.02 V and VDD2,MIN is 4.98 V, resulting in an average regulated VDD2 value of 5.0 V. The resistor divider network may be on-chip (e.g., integrated circuit 1712 or integrated circuit 1718), off-chip (e.g., resistor R1 and resistor R2 are implemented using discrete transistors in package 1702) and/or are external to package 1702 and coupled via one or more pins of package 1702. In at least one embodiment of power transfer device 1600, only one pin (e.g., terminal SNS) is required to control output DC signal VDD2 and a hysteretic band of the voltage regulator of feedback circuit 1608, although in other embodiments, additional pins may be used.

[0040]Referring to FIGS. 16 and 19-21, feedback circuit 1608 includes comparator 1902, which compares voltage VSNS on terminal SNS to reference voltage VREF (e.g., a reference voltage generated by bandgap reference circuit 1612. When comparator 1902 detects that voltage VSNS exceeds first threshold voltage VDD2,MAX, which is based on reference voltage VREF, the output of comparator 1902 changes output signal levels. In typical steady-state operation, (e.g., TSHUT configures lockout circuit 1910 to pass a driven version of the output of comparator 1902), transmitter 1602 communicates the output of comparator 1902 from the secondary side to the primary side across the isolation barrier. The output of comparator 1902 may be converted to a modulated signal for transmission. For example, transmitter 1602 uses oscillator 1610 for on-off keying modulation to communicate a digital representation of the output of comparator 1902 across capacitive channel 1606 to receiver 1604. The primary side generates ENABLE/DISABLE_B based on the received digital signal and controls oscillator circuit 402 accordingly (e.g., disables cascode transistors in oscillator circuit 402 to pause power transfer). When oscillator circuit 402 is disabled, load 1650 on the secondary side starts to discharge capacitor C1. As a result, the voltage level of output DC signal VDD2 drops at a rate equal to

dVDD 2 dt = - I load C 1 .

After me voltage level of output DC signal VDD2 crosses second threshold voltage VDD2,MIN, comparator 1902 changes the level of its output signal. The change in voltage level is communicated from the secondary side to the primary side across the isolation barrier. That change in level causes the primary side to enable oscillator circuit 402, which causes the voltage level of output DC signal VDD2 to ramp up again. Output DC signal VDD2 may have a small AC ripple at twice the oscillator frequency caused by the rectifier. That AC ripple is present only when the oscillator is on and when the voltage level of output DC signal VDD2 is ramping up to first threshold voltage VDD2,MAX. An inherent delay of the received ON and OFF signals generated by on-off keying signaling causes a small DC offset of output DC signal VDD2 that may be reduced by reducing delay of the feedback channel.

[0041]Referring to FIGS. 16 and 19, the reference voltage VREF and the ratio of resistances of resistor R1 and resistor R2 determines the voltage level of output DC signal

V DD 2 since V DD 2 = V REF × ( R 1 + R 2 ) R 2 .

Hysteretic thresholds, first threshold voltage VDD2,MAX and second threshold voltage VDD2,MIN are programmed to target levels using a current I1 that is sourced by p-type transistor 1904 or sunk by n-type transistor 1906 to/from the resistor network including resistor R1 and resistor R2:

V DD 2 , MA X = V ref ( R 1 + R 2 ) R 2 + l 1 R 1 V DD 2 , MI N = V ref ( R 1 + R 2 ) R 2 - l 1 R 1 .

Accordingly, a hysteretic band of the feedback signal is controlled independently of the voltage level of output DC signal VDD2 by using analog techniques: VHYS=VDD2,MAX−VDD2,MIN=2×I1×R1. Oscillator circuit 402 provides a fixed DC current to the secondary side and the load capacitor. At steady state, when the voltage level of output DC signal VDD2 moves between first threshold voltage VDD2,MAX and second threshold voltage VDD2,MIN, capacitor C1 charges at a constant rate of approximately

dVDD 2 dt = I out - I load C 1

and discharges at a constant rate of approximately

dVDD 2 dt = - I load C 1 .

At steady-state,

dVDD 2 dt = V HYS .

Therefore,

[0042] t off = C 1 × V HYS I load

and the frequency of enabling and disabling of oscillator circuit 402 to achieve voltage regulation is

1 t on + t off ,

which is a function of C1, VHYS, and Iload, and may vary according to particular manufacturing conditions. The frequency of feedback channel may be adjusted by selecting appropriate values for C1 and VHYS for particular load conditions.

[0043]Referring to FIG. 20, in at least one embodiment of feedback circuit 1608, rather than using current sources, resistor R3, is included in addition to resistor R1 and resistor R2:

V DD 2 , M AX = ( R 1 R 2 + R 1 R 3 + R 2 R 3 ) V ref R 2 R 3 , and V DD 2 , M IN = V ref ( R 1 R 2 + R 1 R 3 + R 2 R 3 ) ( R 1 + R 3 ) R 2 .

Contrary to the embodiment described above where the average voltage level of output DC signal VDD2 is defined by

V REF × ( R 1 + R 2 ) R 2

with a symmetrical hysteresis band VHYS=2×I1×R1 evenly distributed around the average voltage level of output DC signal VDD2, the upper and lower hysteresis thresholds of the embodiment of FIG. 20 are defined by more elaborate equations that are more complex to calculate. Nevertheless, the circuit provides the target upper and lower hysteretic thresholds using a simpler implementation. Resistor R3 may be included internally to the integrated circuit while resistor R1 and resistor R2 remain external to allow programmability of the hysteretic band and output voltage level using a single pin of the device by selection of first resistance of resistor R1 and second resistance of resistor R2.

[0044]Referring to FIG. 16, in at least one embodiment of power transfer device 1600, thermal shutdown circuit 1618 and thermal shutdown circuit 1620 protect power transfer device 1600 from over-temperature events, which may occur due to ambient temperature being out of a specified range, or due to a fault in power transfer device 1600. Thermal shutdown circuit 1618 generates a primary-side thermal shutdown control signal in response to the temperature on a primary side integrated circuit exceeding a predetermined junction temperature (e.g., 150 C). The primary-side thermal shutdown control signal may be used by timer/oscillator enable circuit 1622 to disable oscillator circuit 402, which is the predominate source of power dissipation of power transfer device 1600. While oscillator circuit 402 is disabled, the junction temperature of power transfer device 1600 decreases, thereby protecting devices of the primary side. Similarly, on the secondary side, thermal shutdown circuit 1620 generates a corresponding thermal shutdown control signal in response to the temperature on the secondary side integrated circuit exceeding a predetermined junction temperature (e.g., 150 C). A secondary-side thermal shutdown control signal may be used by feedback circuit 1608 to provide a feedback signal that, when transmitted across the isolation channel, disables oscillator circuit 402, thereby allowing the junction temperature of power transfer device 1600 to decrease and protect devices on the secondary side. The primary side and the secondary side can cause a thermal shutdown of oscillator circuit 402 independently.

[0045]Referring to FIG. 16, in at least one embodiment of power transfer device 1600, undervoltage lockout circuit 1614 and undervoltage lockout circuit 1616 reduce or eliminate erroneous operation during device startup and device shutdown, or when input DC signal VDD1 has a level below its specified operating range. The primary side and secondary side can cause power transfer device 1600 to enter or exit an undervoltage lockout state independently. Undervoltage lockout circuit 1614 prevents false turn-on or false turn-off of oscillator circuit 402. Undervoltage lockout circuit 1614 generates a gating signal using a voltage detector that detects if the voltage level of input DC signal VDD1 is stable and has crossed a predetermined threshold voltage. Gating logic on the primary side generates gating signal VDD1_OK, which is used by thermal shutdown circuit 1618 to configure circuitry to reduce or eliminate excessive transient currents when the power supply is still coming up and has not yet stabilized. Gating all logic on the primary side with gating signal VDD1_OK reduces or eliminates incorrect decisions made in the control path due to low supply voltage from turning off oscillator circuit 402. Similarly, on the secondary side, undervoltage lockout circuit 1616 monitors output DC signal VDD2. If the voltage level of output DC signal VDD2 crosses a predetermined threshold voltage, undervoltage lockout circuit 1616 generates control signal VDD2_OK that is used by thermal shutdown circuit 1620 to enable the output of feedback circuit 1608 to regulate the voltage level of output DC signal VDD2.

[0046]In at least one embodiment, power transfer device 1600, oscillator circuit 402 includes the LC tank-based oscillator having a cross-coupled n-type transistor latch, as described above, which limits the peak current that can flow through transformer 209. When the secondary side is shorted to ground due to a fault, the peak current limitation of oscillator circuit 402 reduces or eliminates excessive current draw from an input node providing input DC signal VDD1. Those limits on the peak current are described as follows:

Ipeak primary = 2 × V DD 1 2 π f 0 L ( 1 - k 2 ) + R s ; and Ipeak secondary = k × 2 × V DD 1 2 π f 0 L ( 1 - k 2 ) + R s ,

where k is the mutual inductance of the transformer, and RS is the equivalent series resistance of the primary winding. In an exemplary embodiment, the inductance of conductive coil 206, L=100 nH, the fundamental frequency of oscillator circuit 402, f0=75 MHz, and k=0.6, and RS=1.4Ω. Accordingly, Ipeakprimary is approximately 316 mA and Ipeaksecondary is approximately 200 mA.

[0047]In at least one embodiment, power transfer device 1600, includes timer/oscillator enable circuit 1622 on the primary side. Timer/oscillator enable circuit 1622 improves fault tolerance of power transfer device 1600 in response to malfunctioning of the feedback channel. The feedback channel may be inoperative in response to a fault condition on the secondary side or if the load is pulled to ground via a small, finite resistance causing the oscillator circuit 402 to continuously transfer power to the secondary side. The continuous transfer of power from the primary side to the secondary side could cause heating of a secondary side integrated circuit that impacts reliability of the secondary side integrated circuit. For example, excessive junction heating on the secondary side causes thermal shutdown of the secondary side, but transmitter 1602 may be unable to transmit the shutdown signal to the primary side due to a common-mode transient event or fault condition. To reduce or eliminate overstress of devices on the secondary side, timer/oscillator enable circuit 1622 monitors the received feedback signal for a predetermined period of time (e.g., 10 ms). In at least one embodiment, timer/oscillator enable circuit 1622 includes a counter that counts the number of transitions of the received enable/disable feedback control signal provided by receiver 1604 and compares the count to a predetermined threshold count, after the predetermined period. If and insufficient number of transitions of the received feedback signal level occur during that period, timer/oscillator enable circuit 1622 disables oscillator circuit 402 for a second predetermined period (e.g., 10 ms). After expiration of the second predetermined period, timer/oscillator enable circuit 1622 resets. Timer/oscillator enable circuit 1622 continues to monitor and respond any insufficient number of transitions of the received feedback signal until the fault condition disappears and the communications channel and received feedback signal become active again.

[0048]In at least one embodiment, power transfer device 1600, includes overvoltage protection circuit 1624 on the secondary side to reduce or eliminate driving a load with a voltage level of output DC signal VDD2 that exceeds reliability specifications. For example, a fault may cause the communications channel to malfunction and not update the received feedback signal, which causes oscillator circuit 402 to transfer power for a longer period than necessary to charge capacitor C1 to a voltage level corresponding to first threshold voltage VDD2,MAX and thereby causes the voltage level of output DC signal VDD2 to exceed the voltage level corresponding to first threshold voltage VDD2,MAX (e.g., voltages of 9 V for a 5 V VDD2,MAX). Such excessive voltage on the secondary side could damage a device in the load. To reduce or eliminate the likelihood of excessive levels of output DC signal VDD2, overvoltage protection circuit 1624 draws any excess current on the secondary side and sinks that excess current to ground, thereby clamping the voltage level of output DC signal VDD2 and preventing it from further rise. In at least one embodiment, overvoltage protection circuit 1624 includes an active shunt regulator that is configured as an active clamp. An exemplary shut regulator is implemented using feedback circuit techniques that create a scaled version of reference voltage VREF (e.g., 1.1×VREF) and compares that scaled version of reference voltage VREF to voltage VSNS using an error amplifier. The output of the error amplifier activates a clamping device if voltage VSNS exceeds the scaled version of reference voltage VREF. That clamping device shunts the excess current to ground and regulates voltage VSNS to be approximately equal to the voltage level of the scaled version of reference voltage VREF, thereby preventing the voltage level of output DC signal VDD2 from rising further. The scaled version of reference voltage VREF sets the active clamping level to be approximately 10% above the nominal voltage level of output DC signal VDD2, which is within the reliability limits of an external load. For example, if the target voltage level for output DC signal VDD2 is 5V, the active clamp engages when the voltage level of output DC signal VDD2 exceeds 5.5V. During normal operation (i.e., a no-fault mode of operation), voltage VSNS is less than 1.1×VREF and the shunt device is inactive in that state. The active clamp may be disabled while the voltage level of output DC signal VDD2 ramps up (e.g., during a power-up sequence) and may only be enabled when the voltage level of output DC signal VDD2 is close to its regulated voltage level and VDD2_OK indicates no fault condition.

[0049]While circuits and physical structures have been generally presumed in describing embodiments of the invention, it is well recognized that in modern semiconductor design and fabrication, physical structures and circuits may be embodied in computer-readable descriptive form suitable for use in subsequent design, simulation, test or fabrication stages. Structures and functionality presented as discrete components in the exemplary configurations may be implemented as a combined structure or component. Various embodiments of the invention are contemplated to include circuits, systems of circuits, related methods, and tangible computer-readable medium having encodings thereon (e.g., VHSIC Hardware Description Language (VHDL), Verilog, GDSII data, Electronic Design Interchange Format (EDIF), and/or Gerber file) of such circuits, systems, and methods, all as described herein, and as defined in the appended claims. In addition, the computer-readable media may store instructions as well as data that can be used to implement the invention. The instructions/data may be related to hardware, software, firmware or combinations thereof.

[0050]Thus, a power transfer device having an integrated transformer, a relatively small size, high efficiency, and with built-in fault tolerance, and programmable output voltage, voltage ripple, and frequency of DC/AC power conversion has been described. The description of the invention set forth herein is illustrative, and is not intended to limit the scope of the invention as set forth in the following claims. For example, while the invention has been described in embodiments of a power transfer device, techniques described herein may be combined with other isolation products, e.g., digital isolators, analog isolators, and gate drivers in the same package. Variations and modifications of the embodiments disclosed herein, may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.