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Efficient architecture and method for arithmetic computations in post-quantum cryptography

a post-quantum cryptography and efficient architecture technology, applied in computation using non-denominational number representations, instruments, digital transmissions, etc., can solve the problems of large hardware or processing footprint, commercial impracticality, and inability to utilize such methods and systems, and achieve small processing footprint, small processing area, and reduced processing footprint in cryptosystems

Active Publication Date: 2021-10-14
PQSECURE TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The invention provides a system and method for reducing the processing footprint in cryptosystems utilizing quadratic extension field arithmetic. It achieves this by implementing a protocol with a much smaller processing footprint. The system includes a circular-access register file with three registers and a small accelerator for quadratic extension field arithmetic. The method involves performing these arithmetic operations with as small processing area as possible, reducing the processing area, the necessary power and energy for computing various cryptographic primitives. The invention minimizes the number of registers needed to hold intermediate values, minimizes the register complexity, minimizes the number of arithmetic operations required for extension field arithmetic, and selects small arithmetic units to perform extension field arithmetic. The technical effects of the invention are reduced processing footprint, minimized resource footprint, and reduced power and energy for computing various cryptographicprimitives.

Problems solved by technology

Due to the typical amount and time of computations required for a cryptography session, namely one utilizing post-quantum cryptography, the hardware or processing footprint is quite expansive.
As such, utilizing such methods and systems is made impossible or commercially impracticable when desired for use in smaller devices, such as IoT devices.
Therefore, those known systems and methods fail to address small implementations of post-quantum cryptosystems, particularly those which utilize quadratic extension field arithmetic.
As these cryptosystems have only just been gaining popularity and acceptance in the cryptographic community, implementations of arithmetic computations for cryptosystems have also made its deployment problematic.
More specifically, the primary deficiency with post-quantum cryptosystems has typically been their efficiency.
These efforts, however, have resulted in the creation of systems generating large processing footprints that are often inefficient.
As discussed above, however, these configurations are spatially inefficient and not commercially practicable when smaller devices are the targeted implementation environment.
As such, there are no known lightweight implementations of elliptic curve or post-quantum cryptography.
Other known implementations of finite-field arithmetic that attempt to target a small processing footprint environment are not versatile and still commercially impracticable in that they utilize binary fields and elliptic curve cryptography.

Method used

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Embodiment Construction

[0025]While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the drawing figures, in which like reference numerals are carried forward. It is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms.

[0026]The present invention provides a novel and efficient system and method for reducing the processing footprint of arithmetic computations for cryptosystems. More specifically, the system and method is directed toward a cryptosystem having a lightweight accelerator for arithmetic operations in Fp2 (hereinafter “Fp2 accelerator”) containing p2 elements, wherein “p” is a prime number, preferably a constant prime number for which Fp2 field is defined. The system is lightweight in that it is structurally and operably configured to minim...

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Abstract

A computer processing system for reducing a processing footprint in cryptosystems utilizing quadratic extension field arithmetic such as pairing-based cryptography, elliptic curve cryptography, code-based cryptography and post-quantum elliptic curve cryptography that includes at least one computer processor having a register file with three processor registers operably configured to implement quadratic extension field arithmetic equations in a finite field of Fp2 and a multiplexer operably configured to selectively shift from each of the three processor registers in sequential order to generate modular additional results and modular multiplication results from the three processor registers.

Description

FIELD OF THE INVENTION[0001]The present invention relates generally to systems and methods directed toward post-quantum cryptosystems, and, more particularly, relates to cryptosystems utilizing quadratic extension field arithmetic such as pairing-based cryptography, elliptic curve cryptography, code-based cryptography and post-quantum elliptic curve cryptography.BACKGROUND OF THE INVENTION[0002]Cryptology is the practice and study of techniques for secure communication in the presence of third parties called adversaries. More generally, cryptography is about constructing and analyzing protocols that prevent third parties or the public from reading private messages and includes various aspects in information security such as data confidentiality, data integrity, authentication, and non-repudiation. Applications of cryptography include electronic commerce, chip-based payment cards, digital currencies, computer passwords, and military communications. Cryptosystems are a suite of crypto...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H04L9/30G06F7/72H04L9/08
CPCH04L9/3073H04L9/0852G06F7/726H04L9/003H04L2209/122H04L9/3093H04L9/304G06F7/724
Inventor KOZIEL, BRIAN C.LANGENBERG, BRANDON
Owner PQSECURE TECH LLC
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