Semiconductor device capable of accurately producing internal multi-phase clock signal

Abstract

An operation control signal for an oscillator producing an internal clock signal phase-locked with a basic clock signal is applied to a second internal clock generating circuit. In the second internal clock generating circuit, with reference to the applied operation control signal, a control signal adjusting a phase and / or frequency difference between a synchronization target signal and a second internal clock signal is produced to adjust a phase and / or frequency of the second internal clock signal. A plurality of internal clock signals different in phase and / or frequency can be generated accurately and stably.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to a semiconductor device including a circuit for producing an internal clock signal phase-locked with an external clock signal, and more particularly to a semiconductor device producing a plurality of internal clock signals at least having different phases.2. Description of the Background ArtIn clock synchronous type devices, data transfer and processing is performed in synchronization with a clock signal. In such clock synchronous type devices, an internal clock signal synchronized with an external system clock, for example, is generated and a variety of internal operations are performed in synchronization with the internal clock signal. In a field of communication, for example, an internal clock signal is generated by reproducing a clock signal from received data, and the received data is processed in synchronization with this internal clock signal, or at the time of data transmission, data is sent ...

AI Technical Summary

Benefits of technology

An object of the present invention is to provide a semiconductor device capable of accurately generating plural kinds of internal clock signals with a small occupying area.

The clock control signal of the first internal clock generating circuit is applied to the second internal clock generating circuit, and in the second internal clock generating circuit, with reference to the first control signal applied from the first internal clock generating circuit, a signal controlling the operation speed of the second clock generating circuit is produced. Therefore, the second internal clock generating circuit operates in a frequency / phase region of the clock signal generated by the first internal clock generating circuit to produce the internal clock signal and thereafter sets the frequency / phase of the second internal clock signal finally in accordance with the phase difference / frequency difference between the synchronization target signal and the output clock signal. Therefore, even when this synchronization target signal and the basic clock signal have different phases and frequencies, the second internal clock signal synchronized with the synchronization target signal can be produced fast and accurately in the second internal clock generating circuit.

Furthermore, when the first internal clock generating circuit attains a state in which a clock is stably generated, the second internal clock generating circuit enters a locked state at high speed, thereby generating a plurality of internal clock signals stably. In addition, the stabilization timings of the internal clock signals are interrelated with each other, and the stabilization of the internal clock signals is achieved at a faster timing as compared with a case where internal clock signals are generated separately.

Problems solved by technology

In this case, although the phases / frequencies of the signals / data are close to each other, an internal clock signal from one PLL circuit cannot be used to accurately take in these signals / data.

In particular, when a transfer is performed in synchronization with a fast clock signal, an effect of a small phase / frequency shift is increased to make it difficult to take in signals / data accurately.

Therefore, when an oscillation frequency of one phase locked circuit is stable, an oscillation frequency of another phase locked circuit is not always stable, resulting in that a long time is required to stabilize the oscillation frequency in each of the phase locked circuits.

Images