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Photonic input/output port

a technology of input/output ports and photonics, applied in the field of integrated optics, can solve the problems of i/o ports that compromise the overall performance or flexibility of circuits, devices such as i/o ports, manufactured on the same wafers cannot be properly tested, and complicated efforts to commercialize effective telecommunication systems

Inactive Publication Date: 2006-04-18
CISCO TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0030]The present I / O ports, which are suitable for incorporation into a photonic circuit, comprise (1) a layered structure comprising (a) an unpatterned superstrate having at least one layer, (b) an unpatterned substrate having at least one layer and (c) at least one intermediate layer sandwiched between the unpatterned superstrate and the unpatterned substrate, (2) a coupling region that is within the at least one intermediate layer and that comprises an arrangement of at least one optical scattering element and (3) at least one output waveguide to direct (that is, propagate) output light from the coupling region to another part of the photonic circuit. The present I / O ports can be effectively used in balanced photonic circuits and unbalanced photonic circuits.
[0034]c) controlling (for example, maximizing) the in- and out-coupling of a Gaussian-like intensity profile, with a mode field diameter of approximately 10 μm or less; and
[0035]d) controlling (for example, reducing) the insertion loss caused by, for example, a mismatch of effective indices across the output boundary(-ies) of the I / O port;
[0036]e) controlling (for example, reducing) the polarization dependence of I / O port characteristics such as insertion loss and transmission delay, which is the time delay incurred by an optical signal travelling through an I / O port.

Problems solved by technology

The problems with such approaches include the need for photonic circuit surfaces of high quality (that is, highly smooth, planar or substantially planar surfaces, which may be prepared by cleaving and / or polishing and through which a photonic signal may pass), and the need for highly accurate mechanical alignment of micro-photonic elements.
Consistently achieving polarization independence in effective axially-coupled planar or substantially planar circuits has proven to be generally difficult and, in some cases, has resulted in I / O ports that compromise a circuit's overall performance or flexibility.
Moreover, devices, such as I / O ports, fabricated on the same wafer cannot be properly tested until after separation into individual elements.
Such testing constraints have further complicated efforts to commercialize effective telecommunication systems.
Such prior work has suffered from limited coupling bandwidth, insertion loss and / or sensitivity to angular misalignment.
Prior I / O ports designed to couple light at near-normal incidence typically suffer from excessive polarization dependence.
Such suggested solutions are unacceptable for one or more reasons, including, the tendency for such micro-optical elements to move (physically) over time, the cost of assembling those complex systems and the lower yields typically attributable to complex fabrication sequences.

Method used

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[0038]The present I / O ports comprise a planar or substantially planar layered structure comprising an unpatterned superstrate having at least one layer, an unpatterned substrate having at least one layer and at least one intermediate layer, which is sandwiched between the unpatterned superstrate and the unpatterned substrate, a coupling region that is within the at least one intermediate layer and that comprises a pattern of at least one optical scattering element and at least one output waveguide to direct output light from the coupling region to another part of the photonic circuit. In operation, the coupling region is illuminated by external optical input (for example, input light from a fiber). From the coupling region, the light is directed (that is, propagated) to the at least one output waveguide, and, in some embodiments of the present I / O ports, the directing of that light is effected by at least one output region, which, like the rest of the elements comprising the presen...

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Abstract

The present I / O ports comprise (1) a layered structure comprising (a) an unpatterned superstrate having at least one layer, (b) an unpatterned substrate having at least one layer, and (c) at least one intermediate layer sandwiched between the unpatterned superstrate and the unpatterned substrate, (2) a coupling region that is within the at least one intermediate layer and that comprises an arrangement of at least one optical scattering element and (3) at least one output waveguide. The present I / O ports can be effectively used in balanced photonic circuits and unbalanced photonic circuits.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of U.S. patent application Ser. No. 10 / 821,008 filed on Apr. 7, 2004, which is a continuation of Ser. No. 10 / 109,302, filed Mar. 28, 2002, U.S. Pat. No. 6,788,847, which relates to and claims priority benefits from U.S. Provisional Patent Application Ser. No. 60 / 281,650, filed Apr. 5, 2001, which is incorporated by reference herein in its entirety, from U.S. Provisional Patent Application Ser. No. 60 / 302,256, filed Jun. 29, 2001, which is incorporated by reference herein in its entirety and from U.S. Provisional Patent Application Ser. No. 60 / 332,339, filed Nov. 21, 2001, which is incorporated by reference herein in its entirety.FIELD OF THE INVENTION[0002]This invention is related to the field of integrated optics (that is, integrated photonics). In particular, the present devices are photonic input / output (I / O) ports designed for effective coupling of optical signals from a planar photonic circuit to a...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G02B6/12G02B6/00G02B6/30G02B5/02G02B5/18G02B6/122G02B6/124G02B6/126G02B6/132G02B6/42
CPCB82Y20/00G02B6/1225G02B6/124G02B6/132G02B6/30G02B6/423G02B6/126G02B2006/1215
Inventor PADDON, PAUL J.JACKSON, MICHAEL K.YOUNG, JEFF F.LAM, SELENA
Owner CISCO TECH INC