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Trellis construction based on parity check matrix for BCH code

a parity check and bch code technology, applied in the field of optimal trellis diagram, based on parity check matrix for bch encoding, can solve the problem that the construction of optimal bch decoding diagrams has not been disclosed

Inactive Publication Date: 2007-09-04
LEGEND SILICON
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  • Abstract
  • Description
  • Claims
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Benefits of technology

"The invention provides a method and system for creating a trellis diagram that uses BCH-coded information and a parity check matrix to create an ordered sequence of code word transitions. The trellis diagram has a central location and connects n+1 stages, with each stage having at least one state and a corresponding number of input branches. The number of states in a stage is determined by a sum of a corresponding state and a product of the matrix and a sub-code word bit value. The trellis diagram is constructed so that no state has more than two input branches or output branches. The technical effect of the invention is to provide a more efficient and reliable method for creating a trellis diagram for data transmission and processing."

Problems solved by technology

However, construction of a trellis diagram for optimal BCH decoding has not been disclosed.

Method used

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  • Trellis construction based on parity check matrix for BCH code
  • Trellis construction based on parity check matrix for BCH code
  • Trellis construction based on parity check matrix for BCH code

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Embodiment Construction

[0013]Among 64 bits generated in an encoder, the first 57 MSB bits are message bits that have been received by the encoder, which may have the structure illustrated in FIG. 2. After these 57 input bits have been issued as output bits, the next 6 bits, stored at the registers 0-5, are issued as output bits. The last (64th) output bit is the modulo-2 sum of the first 63 bits.

[0014]A Bose-Chaudury-Hocquenheim (BCH) error detection and correction code, such as BCH(64,57) with 7 error check bits, is generated by a particular generator polynomial, such as p(x)=x6+x+1, with an encoder structure illustrated in FIG. 2, where the first 57 bits are received as an input signal by the encoder. The encoder provides a 64-bit output signal, including 6 supplementary bits for error check and a final bit that is a modulo-2 sum of the first 63 bits. More generally, one can specify a linear block code C, using a k×n generator matrix G over GF(2)

[0015]G=[g1g2…gk]=[g11g12…g1⁢Ng21g22…g2⁢N…gk1gk2…gkN](1)

wh...

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Abstract

A method for constructing a simplified trellis diagram for BCH-encoded information is disclosed. BCH-encoded information is received, having a corresponding parity check matrix H. The parity check matrix H is expressed as an ordered sequence of columns of matrices. A sequence of sub-code words is provided, corresponding to one or more code words, each satisfying a given condition. A matrix Hcp, having columns that are generated as a selected permutation of the columns of the matrix H through a column-permutation-for-binary-matching process, is provided, and a sequence of sub-matrices and a corresponding sequence of permuted sub-code words is provided. A trellis diagram, representing an ordered sequence of code word transitions in the received information and symmetric about a central location, is provided for each code word c, connecting n+1 stages, numbered i=0, 1, . . . , n, in an ordered sequence.

Description

FIELD OF THE INVENTION[0001]This invention relates to construction of an optimal trellis diagram, based on a parity check matrix for BCH encoding for error detection.BACKGROUND OF THE INVENTION[0002]A product code is a multi-dimensional array of (n,k) linear block code that exploits a simple and relatively efficient method to construct more powerful codes using linear block code structures. FIG. 1 illustrates construction of a two-dimensional block product code, using a k1×k2 array of data to be encoded.[0003]In the encoding, each row of k2 data values is augmented to include n2−k2 parity check bits for the data in that row; and each column of k1 data values is augmented to include n1−k1 parity check bits for the data in that column. The (n1−k1)×(n2−k2) region at the lower right of this block contains parity check bits for each of the n2−k2 columns above and for each of the n1−k1 rows to the left. Where, for example, a 64QAM configuration is adopted, k1=k2=57 and n1=n2=63. Because 5...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H04L1/14
CPCH03M13/152H04L1/0058H03M13/3944
Inventor ZHONG, YANYANG, LIN
Owner LEGEND SILICON
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