Test pattern for trench poly over-etched step and formation method thereof
a polysilicon and test pattern technology, applied in the direction of semiconductor/solid-state device testing/measurement, electrical equipment, basic electric elements, etc., can solve the problems of profilometry not being surface profilometry may also not be able to obtain the correct, etc., to achieve the effect of increasing the scanning length, increasing the conventional width of the trench, and prolonging the scanning length
Active Publication Date: 2018-05-01
CSMC TECH FAB2 CO LTD
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Benefits of technology
The proposed test pattern configuration allows for a longer scanning length, resulting in clear and accurate scan results for polysilicon trench depth measurements, overcoming the limitations of conventional methods by maintaining a consistent trench width without affecting polysilicon growth.
Problems solved by technology
If the width of the test pattern (i.e. the trench) is too small, the surface profilometry may not able to acquire correct scanning parameters, if the width is too large, the polysilicon will grow into a shape with a higher sidewall and a lower middle portion due to the filling feature of the ploysilicon in the trench, such that the surface profilometry may also not able to obtain the correct result.
Accordingly, due to the limitation of the width of the test pattern, the current test pattern can not be too wide, while the surface profilometry can not obtain the correct scanning parameters under the current width.
Method used
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[0025]Reference will now be made to the drawings to describe, in detail, embodiments of the present invention. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the views.
[0026]FIG. 1 is a schematic, top view of a conventional test pattern. The test pattern shown in FIG. 1 is formed on a test area of a silicon substrate by etching. After the etching back of the polysilicon, the test pattern on the test area is scanned by a surface profilometry to determine the depth of the test area. As shown in FIG. 1, the conventional test pattern is a concave trench, and a plurality of trenches are formed on the silicon substrate 1. FIG. 2 is a schematic cross-sectional view taken along line A-A of FIG. 1. As shown in FIG. 2, the trench has a width 12 and a depth 11. A depth difference H1 ...
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A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench (14) formed on a substrate (1); the trench (14) comprises a bottom surface and two side surfaces extending from the bottom surface; the trench (14) is formed on the substrate (1) with a preset angle of non-90° formed between the longitudinal direction (L) thereof and the longitudinal direction (X) of a wafer scribing trench. The test pattern can extend the scanning length of a step scanning equipment without changing the width of the trench.
Description
FIELD OF THE INVENTION[0001]The present invention relates a semiconductor manufacturing method, and more particularly relates to a polysilicon etching back technique.BACKGROUND OF THE INVENTION[0002]In the trench filling process, it is essential to obtain such parameters as the step depth of the trench after etching back the polysilicon (POLY) for process monitoring of the electronic device, e.g. TRENCH POWER MOS et al.[0003]One way to obtain the depth of the step is to slice. Specifically, one wafer is selected from a plurality of wafers, then it is sliced along a direction vertical to the trench, and the depth of the trench is obtained by using microscope and other related equipments.[0004]Another conventional approach is implemented by monitoring a test pattern. Briefly speaking, a test area with respect to the normal manufacturing area is formed during the manufacturing process. The test area has the same trench as the normal manufacturing area, and the required parameters is ob...
Claims
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IPC IPC(8): H01L21/66H01L21/306
CPCH01L21/30604H01L22/30H01L22/12
Inventor BIAN, ZHENG
Owner CSMC TECH FAB2 CO LTD