Semiconductor camera element of contrast strong detection power
A technology for imaging elements and semiconductors, which is applied in the fields of semiconductor devices, electrical components, and electric solid-state devices, and can solve problems such as inability to obtain contrast and inability to perceive contrast.
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Embodiment 1
[0053] Referring to FIG. 1 , a semiconductor imaging device 1 of the present invention includes a pixel array 2 in which a plurality of pixels PX are arranged in a matrix, a readout control circuit 3 , a reset circuit 5 and a power supply circuit 7 .
[0054] The readout control circuit 3 generates a control signal RD for controlling the generation timing of image data in the pixel array 2 . The reset circuit 5 periodically resets the state of the light receiving and detecting elements in each pixel PX. The timing of the reset operation by the reset circuit 5 is controlled by reset signals Rst0 and Rst1 from the readout control circuit 3 . The power supply circuit 7 supplies a power supply voltage Vd and a ground voltage GND to each pixel in the pixel array 2 .
[0055] Fig. 2 is a block diagram illustrating the configuration of each pixel. In Fig. 2, the pixel PX (i, j) of the i-th row and the j-th column (i and j are natural numbers) and its adjacent pixels are given as re...
Embodiment 2
[0076] In Embodiment 2, the structure of the multiplier PU suitable for such signal amplification factor control will be described. In Embodiment 2, a MOS transistor (also referred to as "A-MOS (Adujustable β-MOS) device" below) capable of controlling the amplification factor β according to the input voltage of the control gate is used to realize automatic adjustment of each pixel. A function of the photosensitivity characteristic.
[0077] Referring to FIG. 5, the A-MOS device has the same common gate GR, source SR and drain DR as common MOS transistors, in addition to having a control gate CG in the form of a certain angle to the normal gate.
[0078] FIG. 6 is a schematic diagram of component configuration parameters of an A-MOS device.
[0079] Referring to FIG. 6, the A-MOS device has the gate length Lr of the normal gate GR, the gate width Wr, and the angle θ formed between the normal gate GR and the control gate CG as element configuration parameters.
[0080] 7A and ...
Embodiment 3
[0091] The effective arrangement of the two photodiodes provided for each pixel in the third embodiment will be described below.
[0092] FIG. 9 is a configuration diagram showing an example of a photodiode arrangement according to Embodiment 3. FIG.
[0093] With reference to Fig. 9, with the P-type silicon substrate (P-sub) 20 that forms semiconductor imaging element and the PN junction that forms with the N well 21 that is arranged on the P-type silicon substrate 20, constitute the photoelectric sensor that detects the average light quantity of surrounding area usefulness. Diode PD0.
[0094] Then use the P formed in the N well 21 + type area 22 and with the P + type region 22 formed within the N + The PN junction formed between the region 23 constitutes a photodiode PD1 for detecting the amount of incident light incident on the pixel. In addition, P + type region 22 and N + The impurity concentration of the P-type region 23 is higher than that of the P-type silicon s...
PUM
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