Film electric crystal array having spare signal line, and its manufacturing method
A technology of thin film transistors and backup signals, applied in nonlinear optics, instruments, optics, etc., can solve problems such as short circuit, open circuit, poor flatness, etc.
Inactive Publication Date: 2008-07-16
AU OPTRONICS CORP
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Problems solved by technology
Since there is only a light-emitting layer sandwiched between the spare signal line 40 and the upper electrode layer as a separation, it is easy to cause a short circuit between the spare signal line 40 and the upper electrode layer due to a flaw in the manufacturing process, and then cause the upper electrode layer to contact the pixel electrode layer 24. (the upper electrode layer is connected to the main signal line 30 via the spare signal line 40, and the main signal line 30 is connected to the source electrode 16, and at the same time, the pixel electrode layer 24 is connected to the drain electrode 18, thereby, when the thin film electrode When the crystal is turned on (on), the above-mentioned source 16 and drain 18 are at the same potential, therefore, the upper electrode layer and the pixel electrode layer 24 are at the same potential), resulting in dead pixels
[0010] 2. Restricted by the structural design of thin film transistor 1, please refer to figure 2 , the flatness of the upper surface of the second isolation layer 22 is not good. Therefore, when the spare signal line 40 is made above the second isolation layer 22, it is easy to cause uneven thickness of the spare signal line 40 due to the undulation of the second isolation layer 22. even break
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[0096] Please refer to Figure 3A , is a schematic diagram of the first embodiment of the present invention, showing a thin film transistor 1, main signal line 30 and spare signal line 40, the thin film transistor includes a gate 12, a first isolation layer 14, a source 16 . A drain 18 , a gate channel 20 , a second isolation layer 22 and a pixel electrode layer 24 .
[0097] The gate 12 is fabricated on the upper surface of a glass substrate 10, and the spare signal line 40 is also fabricated on the upper surface of the glass substrate 10, and a predetermined distance is kept from the gate 12 to avoid mutual interference.
[0098] The first isolation layer 14 is fabricated above the glass substrate 10 and covers the above-mentioned gate electrode 12 and the spare signal line 40. At the same time, the first isolation layer 14 includes a first contact window 141 to expose part of the above-mentioned spare signal line. 40 on the upper surface.
[0099] The gate channel 20 is a...
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It is a kind of film electric crystal array that with the standby signal line. It consists of a film electric crystal, a master signal line and a standby signal line. The film electric crystal is on the surface of a glass base plate. The master signal line is source that connects with the film electric crystal electrically, which used for outputting control signal. The standby signal line connects with the master signal line electrically, and forms the gate with film electric crystal at the same time.
Description
technical field [0001] The invention relates to a thin film transistor array, in particular to a thin film transistor array with spare signal lines. Background of the invention [0002] The flat panel display uses a thin film transistor (thin film transistor, TFT) array to control the display of each pixel. The operation of the thin film transistor must be controlled by signal lines and gate lines. Therefore, if the signal line or the gate line is open, it will affect the normal operation of the thin film transistor and cause the pixel to display abnormally. [0003] Please refer to figure 1 , is a top view of a conventional thin film transistor 1 array. Wherein, the width of the signal line 2 is much smaller than the width of the gate line 3 . Therefore, particle pollution in the process environment and heat treatment in the process may easily lead to disconnection of the signal line 2 . In order to solve the above-mentioned problems arising from the disconnection of t...
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IPC IPC(8): G09G3/20G02F1/03
Inventor 林志雄
Owner AU OPTRONICS CORP