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Latent error detection

An error detection, latent technology with applications in error detection/correction, instrumentation, computing, etc.

Inactive Publication Date: 2008-10-01
HEWLETT-PACKARD ENTERPRISE DEV LP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Alternatively, undetected error handling data may never be detected if the data is not requested and / or if the memory location storing the error handling data is overwritten
[0003] However, these undetected or latent errors in redundant processor systems may be preserved unknowingly

Method used

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Embodiment Construction

[0022] Embodiments of latent error detection are described below. The error detection logic is implemented to periodically scan the memory area for potential processing errors and / or potential storage errors. Each bank corresponds to a different processor element of a logical processor in a redundant processor system. When an associated processor element executes a set of instructions and outputs data that differs from the data output of a redundant processor element executing the same set of instructions, a potential processing error may be stored in the memory area. Potential processing errors are detected by comparing data from two or more redundant storage areas to determine the presence of data errors. Correct data can be determined by comparing data from three or more redundant storage areas, and data errors can be eliminated by copying the correct data in place of potential processing errors.

[0023] A latent storage error may be stored in the storage area as a data ...

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Abstract

In an implementation of latent error detection, memory regions that each correspond to a different processor element of a redundant processor system are scanned for latent processing errors maintained as erroneous data. The data maintained in the memory regions is compared to detect a latent processing error in a first memory region. The latent processing error is resolved by copying data from a second memory region into the first memory region where the data maintained in the second memory region is determined to be identical to data maintained in at least a third memory region.

Description

technical field [0001] The present invention relates to latent error detection. Background technique [0002] Implement multiple redundant processor systems as a fault-tolerant system that prevents downtime, interruption of system operations, and avoids data corruption. Multiple redundant processor systems provide continuous application availability and maintain data integrity, such as for stock trading systems, credit and debit card systems, electronic funds transfer systems, travel reservation systems, and the like. In these systems, data processing operations are performed on multiple independent processing elements, and the results are compared with each other to detect processing errors. Redundant processor systems may generate processing errors that are written to memory and stored as erroneous data that remain undetected until an I / O operation is initiated (eg, written to disk or to a communication line). Bad data can also be detected if a separate processing elemen...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/00
CPCG06F11/1666G06F11/1004G06F11/1633
Inventor R·L·贾丁D·L·伯尼克T·A·海内曼J·R·斯穆伦
Owner HEWLETT-PACKARD ENTERPRISE DEV LP