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Reading circuit for reading a memory cell

A storage unit and read circuit technology, applied in the field of read circuits, can solve the problems of long delay, large readout threshold, crosstalk between adjacent bit lines, etc., and achieve the effect of fast and reliable read operation

Inactive Publication Date: 2008-11-05
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the bit line voltage swing is large, it will cause crosstalk between adjacent bit lines, so that a large read threshold is required
However, this will cause a further longer delay

Method used

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  • Reading circuit for reading a memory cell
  • Reading circuit for reading a memory cell
  • Reading circuit for reading a memory cell

Examples

Experimental program
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Embodiment Construction

[0029] In FIG. 1, a memory cell 12 with a single bit line BL, with a reference bit line BL R The configuration of the corresponding reference unit 13 and the associated reading circuit for reading the storage unit 12 and the reference unit 13. Figure 1 also shows a first precharging means 10 for precharging the bit line BL and a first precharging means 10 for precharging the reference bit line BL R Pre-charged second pre-charging device 11 . The current mode sense amplifier 14 and the current mode tri-state buffer 15 constitute a read circuit. sense amplifier 14 from the bit line BL and the reference bit line BL R Currents are received as input signals, read operations are performed on these currents, and the read results are output to the current mode tri-state buffer 15 . The current mode tri-state buffer 15 compares the current sensed from the bit line BL with the current read from the reference bit line BL R read reference current. The tri-state buffer 15 includes a c...

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PUM

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Abstract

A reading circuit comprises a first and second cascode circuit and a first and second current mirror. The first cascode circuit can be connected to a bit line of a memory cell and the second cascode circuit can be connected to a reference bit line of a reference cell. The first output terminals of the first and second cascode circuits are connected to first terminals of the first and second current mirrors, respectively. The second output terminals of the first and second cascode circuits are connected to the second terminals of the second and first current mirrors, respectively. A tri-state buffer is coupled between the second terminals of the first and second current mirrors said buffer having bit invert capabilities.

Description

field of invention [0001] The invention relates to a reading circuit for reading a memory cell having a single bit line and a corresponding reference cell, and also to an integrated circuit comprising a memory having a memory cell and a reference cell. Background technique [0002] The reference cell read technique uses the same non-volatile memory cell as the memory cell selected by the decoded block, and when the selected cell can be written or not written (or has a high or low threshold), the reference cell will always be cancel (low threshold). Thus, the read circuit compares a low threshold cell (which then draws a rated current representative of its physical characteristics) to a cell that may have a low or high threshold depending on how it was previously programmed. Obviously, if the threshold is low, the selected cell will draw essentially the same current as the reference cell, and if the threshold is high, the current drawn will be zero. At the output stage, fro...

Claims

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Application Information

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IPC IPC(8): G11C7/06G11C16/28G11C17/18G11C11/409G11C11/419
CPCG11C11/419G11C7/062
Inventor E·塞温克A·M·M·西斯P·范德斯蒂格M·M·斯托姆斯
Owner NXP BV