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The encapsulation of integrated circuit chip without lead

An integrated circuit and chip packaging technology, applied in the direction of circuits, electrical components, electrical solid devices, etc., can solve the problems of increased cost and reduced production efficiency, and achieve the effect of low manufacturing cost and good frequency characteristics

Inactive Publication Date: 2008-11-12
NANTONG UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the pins are greatly shortened and have good frequency characteristics, the connection of the ball solder pins requires special equipment and corresponding process procedures, which will also reduce the production efficiency and increase the cost.

Method used

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  • The encapsulation of integrated circuit chip without lead
  • The encapsulation of integrated circuit chip without lead
  • The encapsulation of integrated circuit chip without lead

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0029] Firstly, the encapsulation mold 20 is designed and manufactured. Contrasting Fig. 1, this mold is made of polytetrafluoroethylene material, is disc-shaped structure, is provided with a casting groove 21 of a rectangle at its central part, and a die hole 22 is arranged at the center of groove bottom.

[0030] Then design and manufacture the substrate 1, the present embodiment is based on a 0.8 × 0.7mm 2 Encoding chip design. The distribution of positive interconnection lines 4, gold fingers 5 and metal vias 6 on the front side of the substrate is shown in Figure 2, and the distribution of reverse interconnection lines 8, pads 7 and metal vias 6 on the back side of the substrate is shown in Figure 3. It can be seen from the figure that the number of golden fingers 5 on the front side and the number of pads 7 on the back side all surround the chip 3 placed at the center of the front side of the substrate to form a similar rectangular ring.

[0031] After the substrate 1 ...

Embodiment 2

[0034] The packaging mold 20 in this embodiment is the same as the above embodiment, and the substrate 1 is similar to the above embodiment (not shown). Chip is 1.2×1.0mm 2 To decode the chip, brush one side of it with red glue, paste it in the center area 10 of the substrate where the chip is placed, and then bake it in a heating furnace in a nitrogen environment. The heating temperature is controlled at 120°C for 20 minutes.

[0035] Take it out of the furnace after baking, and then bond the integrated circuit chip 3 and the substrate 1, that is, connect one end of the gold wire (bonding wire 2) to the pad on the decoder chip, and the other end to the gold finger 5 on the substrate, see Figure 4 , Figure 5 . All the pads on the chip are connected to all the golden fingers 5 on the substrate correspondingly, and the capping layer 9 is casted after the connection is completed. At this time, put the above-mentioned substrate connected with the chip into the casting tank 21 ...

Embodiment 3

[0037] The packaging mold 20 in this embodiment is basically the same as that in Embodiment 1, except that the casting groove 21 is longer than that in Embodiment 1. The design of the substrate is designed according to the plan of tiling the above two chips of encoding and decoding, the positive interconnection lines and gold fingers on the front side, the anti-interconnection lines and pads on the back side, and the positive and anti-interconnection lines and metallized vias The connections are the same as in Example 1 (the front and back structure diagrams are not drawn).

[0038] Same as the above-mentioned embodiment, the prepared substrate and the chip were connected with red glue, and baked in a heating furnace with a nitrogen environment. The heating temperature was controlled at 130° C. for 25 minutes.

[0039] The baked substrate and chip are taken out of the furnace, and then bonded. Connect one end of the gold wire (bonding wire 2) to the pad on the chip, and the o...

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PUM

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Abstract

This invention relates to one integration circuit chip sealing without wireless, which comprises baseboard, integration circuit chip, several key wire and resin layers, wherein, the baseboard front and back surfaces are distributed with several connection wire and reverse connection wire; the integration circuit chip is set on front of baseboard with weld disc bonding through bonding line and positive wires with other end connected to metal hole; the reverse connection wire other end is as weld disc and the resin layer covers the baseboard front and integration circuit chip. The process method comprises steps of designing and processing mode, baseboard designing, integration circuit chip and baseboard adding, bonding integration circuit chip and baseboard.

Description

technical field [0001] The invention relates to a leadless integrated circuit chip package. Background technique [0002] In addition to placing, fixing, sealing, and protecting the chip, the integrated circuit package also provides a current path to drive the circuit on the integrated circuit chip, distribute the signals on the integrated circuit chip, and take away the heat generated when the chip is working. With the increase of operating speed, coupled with the low operating voltage and the rapid increase of chip pins, the parasitic coupling effect of capacitance and inductance increases rapidly, and some electrical effects in the package that were originally ignored have begun to affect the normal operation of the circuit. Therefore, in addition to meeting the basic electrical connection functions, the requirements of integrated circuit packaging must also be able to solve the signal integrity problems caused by the high frequency / high speed and the increase in the numb...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L23/31H01L21/50H01L21/60H01L21/56
CPCH01L2224/48091H01L2224/45124H01L2224/45144H01L2924/30107H01L2924/01079H01L2924/00014H01L2924/00
Inventor 景为平孙玲孙海燕金丽徐炜炜
Owner NANTONG UNIVERSITY