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Method for parallelly detecting synchronous communication chips

A communication chip and chip technology, which is applied in the direction of electronic circuit testing, measuring electricity, measuring devices, etc., to achieve the effect of shortening the test time, reducing the test cost, and shortening the test time.

Active Publication Date: 2008-12-10
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When it is necessary to use different test vectors for different DUTs, or write different data for each DUT, due to the design specifications of the existing tester and the limitations of the existing testing technology, it is impossible to simultaneously test multiple The chip is tested with different test vectors

Method used

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  • Method for parallelly detecting synchronous communication chips
  • Method for parallelly detecting synchronous communication chips
  • Method for parallelly detecting synchronous communication chips

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Embodiment Construction

[0011] The method for parallel testing of synchronous communication chips of the present invention first divides and stores the different test vectors of all tested components in the memory of the tester according to the clock cycle, and then outputs all the stored data in parallel according to the clock cycle, thereby obtaining multiple tested components Parallel testing of multiple test vectors for components, and pass / fail judgment on them at the same time. Realize the simultaneous testing of different test vectors for multiple chips of synchronous communication chips (see figure 2 ).

[0012] The process of dividing and storing is as follows: the coordinates of the first DUT during each simultaneous measurement are obtained through the tester’s communication with the probe station, and then according to the relative positions of each DUT during the simultaneous measurement, it is possible to calculate the coordinates of each DUT during each simultaneous measurement. The ...

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Abstract

The invention discloses a method for parallel testing of synchronous communication chips. Firstly, different test vectors of all tested components are divided and stored in the data buffer memory of the tester according to the clock cycle, and then all the stored data are output in parallel according to the clock cycle. In this way, the parallel test of various test vectors of multiple DUTs can be obtained, and the pass / fail judgment can be carried out at the same time. The invention can shorten the test time of the chip, reduce the test cost of the chip, and realize the simultaneous test of multiple test vectors of multiple chips of the synchronous communication chip to the greatest extent.

Description

technical field [0001] The invention relates to a method for testing a large-scale integrated circuit synchronous communication chip, in particular to a method for realizing multi-chip parallel testing of a synchronous communication chip. Background technique [0002] For the existing test system, even if multiple synchronous communication chips can be tested simultaneously, the test vectors used for each device under test (DUT, device under test) are completely consistent (such as figure 1 ). When it is necessary to use different test vectors for different DUTs, or write different data for each DUT, due to the design specifications of the existing tester and the limitations of the existing testing technology, it is impossible to simultaneously test multiple The chip is tested with different test vectors. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a method for parallel testing of synchronous communication ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28G01R31/3183
Inventor 武建宏
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP