Stack type chip package with radiation structure

Abstract

The invention discloses a stack package structure with a confluence frame on a lead frame, which includes: a lead frame, a plurality of inner pin groups and outer pin groups arranged face to face and a chip holder, wherein, the chip holder is arranged among the inner pin groups and a height difference is formed between the chip holder and the inner pin groups; at least a confluence frame with an upper surface and a lower surface is positioned between the inner draw feet groups and the chip holder; a multi-chip offset stack structure is formed by the stack of a plurality of chips. The multi-chip offset stack structure is fixedly connected with the a first surface of the chip holder and is electrically connected with the plurality of inner pin groups; and an package body coats the multi-chip offset stack structure, the inner pin groups, the first surface of the chip holder and the upper surface of the confluence frame, and exposes a second surface of the chip holder and the lower surface of the confluence frame and juts the plurality of outer pin groups out of the package body.

Description

technical field [0001] The invention relates to a multi-chip offset stack package structure, in particular to a multi-chip offset stack package with a heat dissipation structure. Background technique [0002] In recent years, three-dimensional (3D) packaging is being carried out in the back-end process of semiconductors, in order to use the least area to achieve relatively large semiconductor integration (Integrated) or memory capacity. In order to achieve this goal, a three-dimensional (Three Dimension; 3D) package has been developed using a chip stacked method. [0003] In the known technology, chips are stacked in such a way that multiple chips are stacked on a substrate, and then a wire bonding process is used to connect the multiple chips to the substrate. Figure 1A It is a schematic cross-sectional view of a known stacked chip package structure with the same or similar chip size. Such as Figure 1A As shown, the known stacked chip package structure 10 , 100 includes ...

AI Technical Summary

Problems solved by technology

However, when the known technology stacks a plurality of chips of different sizes into the stacked chip package structure 10 in the above-mentioned manner, since the size of the chip on the upper layer must be smaller, the stacked chip package structure 10 has the number of stacked chips. limit

[0007] In the above two stacking methods, Figure 1A The method of using the spacer 130 is likely to cause the disadvantage that the thickness of the stacked chip packaging structure 100 cannot be further reduced; and Figure 1B , since the chip size of the upper layer must be smaller, this will cause the problem that the design or use of the chip will be limited

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