Unlock instant, AI-driven research and patent intelligence for your innovation.

Method for evaluating lifespan of integrated circuit chip products

A product life and integrated circuit technology, applied in the field of IC chip product life evaluation, can solve the problems of wrong life, easy aging, uneven internal temperature division, etc., and achieve the effect of accurate life

Inactive Publication Date: 2009-07-01
VIMICRO CORP
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] It can be seen from the above that T stress Using 125°C will result in a smaller life expectancy, if the actual T stress Excessive 125°C higher than the temperature in the oven, such as above 10°C, may also cause the aging mechanism to be inconsistent with the accelerated model, thereby deriving a wrong lifetime
while T use If the above typical values ​​are used, it will also lead to very inaccurate life estimates
[0007] In addition, in the dynamic working mode of the IC, the internal temperature distribution is not uniform, and the place with high local temperature is the most prone to aging

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for evaluating lifespan of integrated circuit chip products

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0020] The present invention will be described in detail below with reference to the drawings and embodiments.

[0021] figure 1 It is a schematic diagram of the present invention using infrared remote sensing technology to detect the surface temperature of the die in IC dynamic working mode.

[0022] Such as figure 1 As shown, the IC chip has a high-temperature area with the highest local temperature in the dynamic working mode. By performing decapsulation (decap) treatment in this high-temperature area and using an infrared detector, the bare chip under the dynamic working mode in this high-temperature area can be measured. temperature.

[0023] The evaluation method of integrated circuit chip product life of the present invention comprises the following steps:

[0024] Step 1: Estimate and locate the area with the highest local temperature of the IC by evaluating the power consumption in the dynamic working mode of the IC;

[0025] Among them, the power consumption eval...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

This invention provides one integration circuit chip product life evaluation method, which comprises the following steps: pre-evaluating positioning chip local area with highest temperature through chip dynamic work mode; processing package removing at the area with highest local temperature; at the package removing area, using infrared remote detecting device to measure bare surface temperature in the constant and high temperature; using the measured chip dynamic work mode bare surface temperature as Abney effect Tuse and Tstress evaluation chip life.

Description

technical field [0001] The invention relates to a method for evaluating the life of an IC (Integrated Circuit, integrated circuit) chip product, in particular to a method for evaluating the life of an IC chip product using high temperature testing. Background technique [0002] At present, in the field of IC chips, the internationally accepted standard is IC HTOL (High Temperature Operating Life Test High Temperature Operating Life) of JP001.01 of JEDEC / FSA (Joint Electronic Device Engineering Council, Joint Electronic Device Engineering Council / Fabless Semiconductor Association, Fabless Semiconductor Association) The test uses the Arrhenius mode (Arrhenius mode) as the thermal acceleration factor (AFT, Acceleration factor due to Temperature): [0003] AFT=exp(EA / k[(1 / T use )-(1 / T stress )]) [0004] where T use and T stress is the junction temperature. [0005] In the actual test process, the temperature in the oven is usually 125°C as T stress , but actually under t...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/00G01R31/28
Inventor 欧阳浩宇胡敏宋鑫欣
Owner VIMICRO CORP