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Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses

A switch and electrode technology, applied in the field of metal oxide semiconductor field effect transistors, can solve the problem of reducing the width of the trench, and achieve the effect of less switching time and switching loss

Inactive Publication Date: 2009-07-15
FAIRCHILD SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the ability to further reduce the trench width is limited by the ability to etch narrow trenches, and the corresponding need to be able to fill this narrow trench with gate electrode material

Method used

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  • Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses
  • Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses
  • Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses

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Embodiment Construction

[0025] Now refer to the attached drawings especially figure 1 , Which shows a schematic cross-sectional view of a prior art trench gated MOSFET device. The MOSFET device 10 includes a drain region 12, a well region 14, a body region 16, a source region 18, a gate region 20, and a trench 24, all of which are formed on a substrate 26.

[0026] More specifically, the N+ type substrate 26 includes an upper layer 26a in which the N-drain region 12 is formed. The P-type well region 14 is located above the drain region 12. A heavily doped P+ body region 16 is defined in the upper surface (not specified) of the upper layer 26a and a part of the well region 14. A heavily doped N + source region 18 is formed in the upper surface of the upper layer 26 a and a part of the well region 14 and near the trench 24. The sidewalls and bottom (not shown) of the trench 24 are lined with a dielectric material 28, such as oxide. The gate region 20 is formed of a conductive material 30, such as doped po...

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Abstract

A semiconductor gate structure includes a shielding electrode and a switching electrode. Portions of a shield electrode are located over the drain region and the well region. The first dielectric layer is located between the shielding electrode and the drain and well regions. Portions of switch electrodes are located over the well region and the source region. A second dielectric layer is located between the switch electrode and the well and source regions. A third dielectric layer is located between the shield electrode and the switch electrode.

Description

[0001] Related patent application references [0002] This patent application claims the priority benefit of U.S. Provisional Patent Application Serial No. 60 / 405,369, which was filed on August 23, 2002. Technical field [0003] The present invention relates to semiconductors, and more specifically, to metal oxide semiconductor field effect transistors (MOSFETs). Background technique [0004] MOSFETs are widely used in the switching field. For example, switching power supplies hardly use other types of transistors. MOSFETs are suitable for such switching applications because they have relatively high switching speeds and require low power. However, the dynamic loss in the MOSFET occupies a large percentage of the total loss of the DC-DC converter. The dynamic loss is proportional to the rise and fall time of the device, and the rise and fall time of the device is in turn proportional to the gate-drain capacitance of the device, which is the Miller capacitance (C GD Or Q GD ) Is pr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/76
CPCH01L29/407H01L29/7813H01L29/41H01L29/42376
Inventor 克里斯托弗·B.·库肯艾伦·艾本海威
Owner FAIRCHILD SEMICON CORP