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Package structure of crystal particle and manufacturing method thereof

A technology of packaging structure and packaging method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as difficulties, time-consuming, and inability to meet the needs of planting bumps on a single chip, and achieve saving The effect of timing

Active Publication Date: 2009-07-29
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It will be difficult and time consuming to plant bumps on a single chip
Therefore, the chip packaging method of the prior art will not be able to meet the needs of planting bumps on a single chip

Method used

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  • Package structure of crystal particle and manufacturing method thereof
  • Package structure of crystal particle and manufacturing method thereof
  • Package structure of crystal particle and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0034] Please refer to Figure 2A to Figure 2C , which represents a schematic diagram of the manufacturing method of the chip according to the present invention. Please refer to Figure 2A , firstly, a flat panel 20 is provided, the flat panel 20 has a first surface 201 and a second surface 202, the second surface 202 is relative to the first surface 201, wherein in an embodiment, the first surface 201 is a circuit surface, and in other In application, the second surface 202 may also be a circuit surface. Then, form a plurality of chips 21 on the first surface 201 of the flat plate 20, the chips 21 have a first surface 211 and a second surface 212, the second surface 212 is relative to the first surface 211, wherein the chips 21 are arranged in an array arranged and adhered on the first surface 201 of the plate 20 by using resin.

[0035] Please refer to Figure 2B , forming a plurality of bumps 22 on the first surface 211 of the chip 21 , wherein a preferred material of t...

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PUM

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Abstract

This invention discloses a package structure of grains and its manufactring method including the following steps: providing a flat with a first surface and a second surface, forming multiple first grains on the first surface of the flat and the first grain has a first surface and a second surface, forming multiple first humps on the first surface of the first grains and cutting the flat to form multiple grain groups, each of which has a flat unit, a first grain and multiple first humps, and the first grain is placed on the first surface of the flat unit so it is easy for single grains to be implanted on the humps.

Description

technical field [0001] The invention relates to a chip packaging method, in particular to a chip packaging structure and a manufacturing method thereof. Background technique [0002] Please refer to Figure 1A to Figure 1C , which represents a schematic diagram of a conventional chip manufacturing method. First, please refer to Figure 1A , a wafer 11 is provided, a plurality of chips 111 are defined in the wafer 11 (shown by dashed lines), and the wafer 11 has a first surface 112 . Please refer to Figure 1B , and then, forming a plurality of bumps 12 on the first surface 112 of the wafer 11 , wherein a preferred material of the bumps 12 is gold. Please refer to Figure 1C , and then, dicing the wafer 11 to form a plurality of chips 111 . [0003] The conventional chip packaging method is to form bumps 12 on the entire wafer 11 , and then cut the wafer 11 into chips 111 . It would be difficult and time consuming to plant bumps on a single chip. Therefore, the chip pa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/00H01L23/488H01L21/50H01L21/60
CPCH01L2224/48091H01L2224/16225H01L2224/73204H01L2224/48227H01L2224/32225
Inventor 戴惟璋李政颖
Owner ADVANCED SEMICON ENG INC