Semiconductor wafer including semiconductor chips divided by scribe line and process-monitor electrode pads formed on scribe line
A semiconductor and scribing line technology, applied in semiconductor/solid-state device testing/measurement, semiconductor device, semiconductor/solid-state device manufacturing, etc., can solve problems such as increased manufacturing costs
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no. 1 example
[0091] Figure 1A and 1B is a schematic illustration for describing a semiconductor wafer 1 according to an embodiment of the present invention. More specifically, Figure 1A To show a plan view near the scribing line of the semiconductor wafer 1, Figure 1B for along Figure 1A A cross-sectional view taken along line A-A. figure 2 It is a plan view showing the overall structure of the semiconductor wafer 1 according to the embodiment of the present invention. Figure 3A and 3B It is a schematic diagram for describing a part of a process monitoring device placed on a scribing line according to an embodiment of the present invention. More specifically, Figure 3ATo show a plan view of a part of the process monitoring device, Figure 3B for along Figure 3A Sectional view taken along line B-B. The semiconductor wafer 1 according to the embodiment of the present invention has a three-layer metal wiring structure.
[0092] Such as figure 2 As shown, a semiconductor w...
no. 2 example
[0138] Figure 16A and 16B is a schematic diagram illustrating a semiconductor wafer 101 according to an embodiment of the present invention. More specifically, Figure 16A To show a plan view near the scribing line 105 of the semiconductor wafer 101, Figure 16B for along Figure 16A Sectional view taken along line A-A. Figure 17 is a plan view showing the overall structure of the semiconductor wafer 101 according to the embodiment of the present invention. 18A and 18B are schematic diagrams for describing a process monitoring device placed on a scribing line according to an embodiment of the present invention. More specifically, FIG. 18A is a plan view showing a portion of a process monitoring device, Figure 18B It is a cross-sectional view taken along line B-B in FIG. 18A. The semiconductor wafer 101 according to the embodiment of the present invention has a three-layer metal wiring layer structure.
[0139] Such as Figure 17 As shown, a semiconductor wafer 101 ...
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Abstract
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